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CoreConnect is a microprocessor bus architecture from IBM for system-on-a-chip (SoC) designs. Designed to ease the integration and reuse of processor, system, and peripheral cores within standard and custom SoC designs. It is a standard SoC design point, and serves as the foundation of IBM or non-IBM devices. Elements of this architecture include the processor local bus (PLB), the on-chip peripheral bus (OPB), a bus bridge, and a device control register (DCR) bus. High-performance peripherals connect to the high-bandwidth, low-latency PLB. Slower peripheral cores connect to the OPB, which reduces traffic on the PLB. There are bridging capabilities to the competing AMBA bus architecture allowing reuse of existing SoC-components.

The CoreConnect bus is available as a no-fee, no-royalty architecture to tool vendors, core IP companies, and chip development companies. As such it is licensed by over 1500 electronics companies such as Cadence, Ericsson, Lucent, Nokia, Siemens and Synopsys.

The CoreConnect is an integral part of IBM's Power Architecture offering and is used extensively in their PowerPC 4x0 based designs. Xilinx uses CoreConnect as the infrastructure for all of their embedded processor designs even though only a few are Power Architecture based.

Processor Local Bus (PLB)

• General processor local bus
• Synchronous, nonmultiplexed bus
• Separate Read, Write data buses
• Supports concurrent Read, Writes
• Multimaster, programmable-priority, arbitrated bus
• 32-bit address
• 32-/64-/128-bit implementations (to 256-bit)
• 66/133/183 MHz (32-/64-/128-bit)
• Pipelined, supports early split transactions
• Overlapped arbitration (last cycle)
• Supports fixed, variable-length bursts
• Bus locking
• High bandwidth capabilities, up to 2.9 GB/s.

On-chip Peripheral Bus (OPB)

• Peripheral bus for slower devices
• Synchronous, nonmultiplexed bus
• Multimaster, arbitrated bus
• 32-bit address
• Separate 32-bit Read, Write buses
• Pipelined transactions
• Overlapped arbitration (last cycle)
• Supports bursts
• Dynamic bus sizing, 8-, 16-, 32-bit devices
• Single-cycle data transfers
• Bus locking (parking)

Device Control Register (DCR) bus

• Provides fully synchronous movement of GPR data between CPU and slave logic
• Synchronous, nonmultiplexed bus
• Separate Read, Write data buses
• Single-master, multiple-slave bus
• 10-bit address bus
• 32-bit data buses
• Two-cycle minimum Read/Write cycles
• Distributed multiplexer architecture
• Supports 8-, 16-, 32-bit devices
• Single-cycle data transfers

See also

• PowerPC 400
• Power Architecture

External links

• CoreConnect bus architecture, IBM.com
• CoreConnect Technology , Xilinx.com
• CoreConnect licensing, IBM.com
• CoreConnect: The On-Chip Bus System, ElectronicDesign.com