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Intel 8087 Math Coprocessor
simplified i8087 microarchitecture.

The Intel 8087, announced in 1980, was the first floating point coprocessor for the 8086 line of processors; it had 45,000 transistors manufactured as a 3 μm depletion load HMOS circuit. (The Intel 8231 was older but designed for the Intel 8080.)

The 8087, the first of the x87 family, was built to be paired with the Intel 8088 and 8086 microprocessors and the purpose was to speed up computations on demanding applications involving floating point arithmethic. The performance enhancements were from appoximately 20% to over 500% depending on the specific application. The 8087 could perform about 50 000 FLOP/s, depending on the operation performed.

This coprocessor introduced about 60 new instructions available to the programmer, their assembly mnemonics all beginning with "F" to differentiate them from the 8086 integer instructions. For example, as a complement to ADD/MUL/CMP the 8087 provided FADD/FMUL/FCOM etc. The binary encodings for all new instructions began with the bit pattern 11011, decimal 27, the same as the ASCII character ESC; similar instruction prefixes are also sometimes referred to as "escape codes" but whether this was the first usage of this term remains unclear.

The x87 family does not use a directly addressable register set such as the main registers of the x86 processors; instead the x87 registers form a 8-level deep stack structure ranging from st0 to st7, where st0 is the top. The x87 instructions operate by pushing, calculating, and popping values on this stack. However, dyadic operations such as FADD, FMUL, FCOM, and so on, may either implicitly use the topmost st0 and st1, or, it may use st0 together with an explicit memory operand or register; the st0 register may thus be used as an accumulator (i.e. as a combined destination and left operand) and can also be exchanged with any of the eight stack registers using an instruction called exch stX (codes D9C8..D9CFh). This makes the x87 stack useable as seven freely addressable registers plus an accumulator. This is especially appliciable on superscalar x86 processors (Pentium of 1993 and later) where these exchange instructions are optimized down to a zero clock penalty (by using one of the integer paths for exch st(x) in parallel with an adjoint FPU instruction).

When Intel designed the 8087 it aimed to make a standard floating point format for future designs. An important aspect of the 8087 from a historical perspective was that it became the basis for the IEEE 754 floating point standard. The 8087 did not implement the eventual IEEE 754 standard in all its details, as the standard wasn't finished until 1985, but the 80387 did. The 8087 provided two basic 32/64-bit floating point data types and an additional extended 80-bit internal temporary format (that could also be stored in memory) to improve accuracy over large and complex calculations. Apart from this, the 8087 offered an 80-bit/18-digit packed BCD (binary coded decimal) format and 16, 32 and 64-bit integer data types.

The 8087 differed from subsequent Intel coprocessors in that it was directly connected to the address and data buses. The 8088/86 looked for instructions that commenced with the '11011' sequence and relinquished control to the coprocessor. The coprocessor handed control back once the sequence of coprocessor instructions ended. There was a potential crash problem if the coprocessor instruction failed to decode to one that the coprocessor understood. Intel's later coprocessors did not connect to the buses in the same way, but were handed the instructions by the main processor. This yielded an execution time penalty, but the potential crash problem was avoided because the main processor would ignore the instruction if the coprocessor refused to accept it. The 8087 was able to detect whether it was connected to a 8088 or a 8086 by monitoring the data bus during the reset cycle.

The 8087 was superseded by the 80287, 80387 and the 80487. Intel 80486DX, Pentium and later processors include a built-in coprocessor on the CPU core.

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