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x86 processor modes
Mode First supported
Intel 8086
Intel 80286
Intel 80386
Intel 80386
Intel 386SL
  • Long mode
AMD Opteron

In the x86-64 computer architecture, long mode is the mode where a 64-bit application (or operating system) can access the 64-bit instructions and registers, while 16-bit protected mode programs that never use neither real mode nor virtual 8086 mode and 32-bit programs are executed in a compatibility sub-mode.



An x86-64 processor acts identically as an IA-32 processor when running in real mode or protected mode, which are supported sub-modes when the processor is not in long mode.

A bit in the CPUID extended attributes field informs programs in real or protected modes if the processor can go to long mode, which allows a program to detect an x86-64 processor. This is similar to the CPUID attributes bit that Intel IA-64 processors use for allowing programs to detect they are running under IA-32 emulation.

Memory limitations

While register sizes have increased to 64-bits from the previous x86 architecture, memory addressing has not yet been increased to the full 64 bits. For the time being, it is impractical to equip computers with sufficient memory to require a full 64 bits. As long as that remains the case, load/store unit(s), cache tags, MMUs and TLBs can be simplified without any loss of usable memory. Despite this limitation, software is programmed using full 64 bit pointers, and will therefore be able to use progressively larger address spaces as they become supported by future processors and operating systems.

Current limits

The first CPUs implementing the x86-64 architecture, namely the AMD Athlon64 / Opteron (K8) CPUs, had 48 bit virtual and 40 bit physical addressing. From the K10, the physical addressing has been increased to 48 bits. The virtual address space of these processors is divided into two 47-bit regions, one starting at the lowest possible address, the other extending down from the largest. Attempting to use addresses falling outside this range will cause a general protection fault.

The physical memory limitation is a limitation on how much RAM you can install in the machine. On a ccNUMA multiprocessor system (Opteron) this includes the memory which is installed in the remote nodes, because the CPUs can directly address (and cache) all memory regardless if it is on the home node or remote. The 1 TiB limit (40bit) for physical memory for the K8 is still huge, but might have been a limit for use in supercomputers. Consequently, the new K10 microarchitecture has a 48 bit physical memory limit (256 TiB).

When there is need, the microarchitecture can be expanded step by step without side-effects from software and simultaneously save cost with its implementation. For future expansion, the architecture supports expanding memory addressing to 56 bits (limited by the page table entry format), which would allow for the processor to access 256 Bytes, or 64 pebibytes.

See also

External links

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