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In electronics, a multi-level cell (MLC) is a memory element capable of storing more than a single bit of information.

MLC NAND flash is a flash memory technology using multiple levels per cell to allow more bits to be stored as opposed to SLC NAND flash technologies, which uses a single level per cell. Currently, most MLC NAND stores four states per cell, so the four states yield two bits of information per cell. This reduces the amount of margin separating the states and results in the possibility of more errors.

MLC NAND has the benefit of being cheaper due to the denser storage method used, but software complexity can be increased to compensate for a larger bit error ratio (BER).[1]

The higher BER requires an algorithm that can correct errors up to five bits and detect the condition of more than five bad bits. The most commonly used algorithm is Bose-Chaudhuri-Hocquenghem (BCH code).

A few memory devices go the other direction, and use two cells per bit, to give even lower bit error rates.[2]

See also


  1. ^ Micron's MLC NAND Flash Webinar
  2. ^ "Automotive EEPROMs use two cells per bit for ruggedness, reliability" by Graham Prophet 2008-10-02

External links


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