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Computer memory types

Phase-change memory (also known as PCM, PRAM, PCRAM, Ovonic Unified Memory, Chalcogenide RAM and C-RAM) is a type of non-volatile computer memory. PRAM uses the unique behavior of chalcogenide glass, which can be "switched" between two states, crystalline and amorphous, with the application of heat. Recent versions can achieve two additional distinct states, effectively doubling its storage capacity. PRAM is one of a number of new memory technologies that are attempting to compete in the non-volatile role with the almost universal Flash memory, which has a number of practical problems these replacements hope to address.



The properties of chalcogenide glasses were first explored as a potential memory technology by Stanford R. Ovshinsky of Energy Conversion Devices in the 1960s. In the September 1970 issue of Electronics, Gordon Moore — co-founder of Intel — published an article on the technology. However, material quality and power consumption issues prevented commercialization of the technology. More recently, interest and research have resumed as flash and DRAM memory technologies are expected to encounter scaling difficulties as chip lithography shrinks.

The crystalline and amorphous states of chalcogenide glass have dramatically different electrical resistivity, and this forms the basis by which data are stored. The amorphous, high resistance state is used to represent a binary 0, and the crystalline, low resistance state represents a 1. Chalcogenide is the same material used in re-writable optical media (such as CD-RW and DVD-RW). In those instances, the material's optical properties are manipulated, rather than its electrical resistivity, as chalcogenide's refractive index also changes with the state of the material.

Although PRAM has not yet reached the commercialization stage for consumer electronic devices, nearly all prototype devices make use of a chalcogenide alloy of germanium, antimony and tellurium (GeSbTe) called GST. The stoichiometry or Ge:Sb:Te element ratio is 2:2:5. When GST is heated to a high temperature (over 600°C), its chalcogenide crystallinity is lost. Once cooled, it is frozen into an amorphous glass-like state and its electrical resistance is high. By heating the chalcogenide to a temperature above its crystallization point, but below the melting point, it will transform into a crystalline state with a much lower resistance. The time to complete this phase transition is temperature-dependent. Cooler portions of the chalcogenide take longer to crystallize, and overheated portions may be remelted. Commonly, a crystallization time scale on the order of 100 ns is used.[1] This is longer than conventional volatile memory devices like modern DRAM, which have a switching time on the order of two nanoseconds. However, a January 2006 Samsung Electronics patent application indicates PRAM may achieve switching times as fast as five nanoseconds.

A more recent advance pioneered by Intel and ST Microelectronics allows the material state to be more carefully controlled, allowing it to be transformed into one of four distinct states; the previous amorphic or crystalline states, along with two new partially crystalline ones. Each of these states has different electrical properties that can be measured during reads, allowing a single cell to represent two bits, doubling memory density.[2]

A cross-section of two PRAM memory cells. One cell is in low resistance crystalline state, the other in high resistance amorphous state.

PRAM vs. Flash

It is the switching time that makes PRAM, and other replacements for flash memory, most interesting. PRAM's temperature sensitivity is perhaps its most notable drawback, one that may require changes in the production process of manufacturers incorporating the technology.

Flash memory works by modulating charge (electrons) stored within the gate of a MOS transistor. The gate is constructed with a special "stack" designed to trap charges (either on a floating gate or in insulator "traps"). The presence of charge within the gate shifts the transistor's threshold voltage, \,V_{th} higher or lower, corresponding to a 1 to 0, for instance. Changing the bit's state requires removing the accumulated charge, which demands a relatively large voltage to "suck" the electrons off the floating gate. This burst of voltage is provided by a charge pump which takes some time to build up power. General write times for common Flash devices are on the order of one ms (for a block of data), about 100,000 times the typical 10 ns read time, for SRAM for example (for a byte).

PRAM can offer much higher performance in applications where writing quickly is important, both because the memory element can be switched more quickly, and also because single bits may be changed to either 1 or 0 without needing to first erase an entire block of cells. PRAM's high performance, thousands of times quicker than conventional hard drives, make it particularly interesting in nonvolatile memory roles that are currently performance-limited by memory access timing.

Additionally, with Flash each burst of voltage across the cell causes degradation. As the size of the cells decreases, damage from programming grows worse because the voltage necessary to program the device does not scale with the lithography. Most flash devices are only rated for something on the order of 10,000 to 100,000 writes per sector, and many flash controllers perform wear leveling to spread writes across many physical sectors.

PRAM devices also degrade with use, for different reasons than Flash, but degrade much more slowly. A PRAM device may endure around 100 million write cycles.[3] PRAM lifetime is limited by mechanisms such as degradation due to GST thermal expansion during programming, metal (and other material) migration, and other mechanisms still unknown.

Flash parts can be programmed before being soldered on to a board, or even purchased pre-programmed. The contents of a PRAM, however, are lost because of the high temperatures needed to solder the device to a board (see reflow soldering or wave soldering). This is made worse by the recent drive to lead-free manufacturing. The manufacturer using PRAM parts must provide a mechanism to program the PRAM "in-system" after it has been soldered in place.

The special gates used in Flash memory "leak" charge (electrons) over time, causing corruption and loss of data. The resistivity of the memory element in PCM is more stable; at the normal working temperature of 85°C, it is projected to retain data for 300 years.[4]

By carefully modulating the amount of charge stored on the gate, Flash devices can store multiple (usually two) bits in each physical cell. This effectively doubles the memory density, reducing cost. PRAM devices originally stored only a single bit in each cell, but Intel's recent advances have removed this problem.

Because Flash devices trap electrons to store information, they are susceptible to data corruption from radiation, making them unsuitable for many space and military applications. PRAM exhibits higher resistance to radiation.

PRAM cell selectors can use various devices: diodes, BJTs and MOSFETs. Using a diode or a BJT provides the greatest amount of current for a given cell size. However, the concern with using a diode stems from parasitic currents to neighboring cells, as well as a higher voltage requirement, resulting in higher power consumption. The chalcogenide resistance being a necessarily larger resistance than the diode entails that the operating voltage must exceed 1 V by a wide margin to guarantee adequate forward bias current from the diode. Perhaps the most severe consequence of using a diode-selected array, particularly for large arrays, is the total reverse bias leakage current from the unselected bit lines. In transistor-selected arrays, only the selected bit lines contribute reverse bias leakage current. The difference in leakage current is several orders of magnitude. A further concern with scaling below 40 nm is the effect of discrete dopants as the p-n junction width scales down.

2000 and later

In August 2004, Nanochip licensed PRAM technology for use in MEMS (micro-electric-mechanical-systems) probe storage devices. These devices are not solid state. Instead, a very small platter coated in chalcogenide is dragged beneath many (thousands or even millions) of electrical probes which can read and write the chalcogenide. Hewlett-Packard's micro-mover technology can accurately position the platter to 3 nanometers so densities of more than 1 Tb (128 GB) per square inch will be possible if the technology can be perfected. The basic idea is to reduce the amount of wiring needed on-chip; instead of wiring every cell, the cells are placed closer together and read by current passing through the MEMS probes, acting like wires. This approach bears much resemblance to IBM's Millipede technology.

In September 2006, Samsung announced a prototype 512 Mb (64 MB) device using diode switches[5]. The announcement was something of a surprise, and it was especially notable for its fairly high density. The prototype featured a cell size of only 46.7 nm, smaller than commercial Flash devices available at the time. Although Flash devices of higher capacity were available (64 Gb, or 8 GB, was just coming to market), other technologies competing to replace Flash generally offered lower densities (larger cell sizes). The only production MRAM and FeRAM devices are only 4 Mb, for example. The high density of Samsung's prototype PRAM device suggested it could be a viable Flash competitor, and not limited to niche roles as other devices have been. PRAM appeared to be particularly attractive as a potential replacement for NOR Flash, where device capacities typically lag behind capities of NAND Flash devices. (State-of-the-art capacities on NAND passed 512 Mb some time ago.) NOR Flash offers similar densities to Samsung's PRAM prototype and already offers bit addressability (unlike NAND where memory is accessed in banks of many bytes at a time).

Samsung's announcement was followed by one from Intel and STMicroelectronics, who demonstrated their own PCM devices at the 2006 Intel Developer Forum in October[6]. They showed a 128 Mb part that recently began manufacture at STMicroelectronics's research fab in Agrate, Italy. Intel stated that the devices were strictly proof-of-concept, but they expect to start sampling within months, and have widespread commercial production within a few years. Intel appears to be aiming their PCM products at the same market as Samsung.

PCM is also a promising technology in the military and aerospace industries where radiation effects make the use of standard non-volatile memories such as Flash impractical. PCM memory devices have been introduced by BAE Systems, referred to as C-RAM, claiming excellent radiation tolerance (rad-hard) and latchup immunity. Additionally, BAE claims a write cycle endurance of 108, which will allow it to be a contender for replacing PROMs and EEPROMs in space systems.

In February 2008, Intel engineers, in cooperation with STMicroelectronics, revealed the first multilevel (MLC) PCM array prototype. The prototype stored two logical bits in each physical cell, effectively 256 Mb of memory stored in a 128 Mb physical array. This means that instead of the normal two states -- fully amorphous and fully crystalline -- an additional two distinct intermediate states represent different degrees of partial crystallization, allowing for twice as many bits to be stored in the same physical area on the chip.[2]

Also in February 2008, Intel and STMicroelectronics began shipping prototype samples of their first PCM product released to customers. The 90nm, 128Mb (16MB) product is called Alverstone.[7]


The greatest challenge for phase-change memory has been the requirement of high programming current density (>107 A/cm2, compared to 105-106 A/cm2 for a typical transistor or diode) in the active volume. This has led to active areas which are much smaller than the driving transistor area. The discrepancy has forced phase-change memory structures to package the heater and sometimes the phase-change material itself in sublithographic dimensions. This is a process cost disadvantage compared to Flash.

The contact between the hot phase-change region and the adjacent dielectric is another fundamental concern. The dielectric may begin to leak current at higher temperature, or may lose adhesion when expanding at a different rate from the phase-change material.

Phase-change memory is susceptible to a fundamental tradeoff of unintended vs. intended phase-change. This stems primarily from the fact that phase-change is a thermally driven process rather than an electronic process. Thermal conditions which allow for fast crystallization should not be too similar to standby conditions, e.g. room temperature. Otherwise data retention cannot be sustained. With the proper activation energy for crystallization it is possible to have fast crystallization at programming conditions while having very slow crystallization at normal conditions.

Probably the biggest challenge for phase change memory is its long-term resistance and threshold voltage drift.[8] The resistance of the amorphous state slowly increases according to a power law (~t0.1). This severely limits the ability for multilevel operation (a lower intermediate state would be confused with a higher intermediate state at a later time) and could also jeopardize standard two-state operation if the threshold voltage increases beyond the design value.


  • September 1966: Stanford Ovshinsky files first patent on phase change technology
  • June 1969: US Patent 3,448,302 licensed to Ovshinsky claims first reliable operation of phase change memory
  • September 1970: Gordon Moore publishes research in Electronics Magazine
  • June 1999: Ovonyx joint venture is formed to commercialize PRAM technology
  • November 1999: Lockheed Martin works with Ovonyx on PRAM for space applications
  • February 2000: Intel invests in Ovonyx, licenses technology
  • December 2000: ST Microelectronics licenses PRAM technology from Ovonyx
  • March 2002: Macronix files a patent application for transistor-less PRAM
  • July 2003: Samsung begins work on PRAM technology
  • 2003 through 2005: PRAM-related patent applications filed by Toshiba, Hitachi, Macronix, Renesas, Elpida, Sony, Matsushita, Mitsubishi, Infineon and more
  • August 2004: Nanochip licenses PRAM technology from Ovonyx for use in MEMS probe storage
  • August 2004: Samsung announces successful 64Mbit PRAM array
  • February 2005: Elpida licenses PRAM technology from Ovonyx
  • September 2005: Samsung announces successful 256Mbit PRAM array, touts 400µA programming current
  • October 2005: Intel increases investment in Ovonyx
  • December 2005; Hitachi and Renesas announce 1.5volt PRAM with 100µA programming current
  • December 2005: Samsung licenses PRAM technology from Ovonyx
  • July 2006: BAE Systems begins selling the first commercial PRAM, a Radiation Hardened C-RAM 512Kx8 chip
  • September 2006: Samsung announces 512Mbit PRAM device
  • October 2006: Intel and STMicroelectronics show a 128Mbit PRAM chip
  • December 2006: IBM Research Labs demonstrate a prototype 3 by 20 nanometers[9]
  • January 2007: Qimonda licenses PRAM technology from Ovonyx
  • April 2007: Intel's chief technology officer Justin Rattner is set to give the first public demonstration of the company's PRAM (phase-change RAM) technology [10]
  • October 2007: Hynix begins pursuing PRAM by licensing Ovonyx' technology
  • February 2008: Intel and STMicroelectronics announce four-state MLC PRAM[2] and begin shipping samples to customers[7].
  • December 2008: Numonyx announces mass production 128Mbit PCM device to selected customer.
  • June 2009: Samsung's phase change RAM will go into mass production starting in June[11]
  • September 2009: Samsung announces mass production start of 512Mbit PRAM device[12]
  • October 2009: Intel and Numonyx announce they have found a way to stack phase change memory arrays on one die[13]
  • December 2009: Numonyx announces 1Gb 45nm product[14]


  1. ^ H. Horii et al.,2003 Symposium on VLSI Technology, 177-178 (2003).
  2. ^ a b c A Memory Breakthrough, Kate Greene, Technology Review, 04-Feb-2008
  3. ^ Intel to Sample Phase Change Memory This Year
  4. ^ Pirovano, A. Redaelli, A. Pellizzer, F. Ottogalli, F. Tosi, M. Ielmini, D. Lacaita, A.L. Bez, R. Reliability study of phase-change nonvolatile memories. IEEE Transactions on Device and Materials Reliability. Sept. 2004, vol 4, issue 3, pp. 422–427. ISSN 1530-4388.
  5. ^ SAMSUNG Introduces the Next Generation of Nonvolatile Memory - PRAM
  6. ^ Intel Previews Potential Replacement for Flash
  7. ^ a b "Intel, STMicroelectronics Deliver Industry's First Phase Change Memory Prototypes". Numonyx. 2008-02-06. Retrieved 2008-08-15.  
  8. ^ D. Ielmini et al., IEEE Trans. Electron Dev. vol. 54, 308-315 (2007).
  9. ^ Phase Change to Replace Flash?
  10. ^ - Intel set for first public demo of PRAM
  11. ^ Engadget Samsung PRAM chips go into mass production
  12. ^ Samsung moves phase-change memory to production
  13. ^ Intel and Numonyx Achieve Research Milestone with Stacked, Cross Point Phase Change Memory Technology
  14. ^ Numonyx to Present Phase Change Memory Research Results at Leading Technology Industry Conference

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