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SDRAM latency: Wikis


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SDRAM latency refers to the delays incurred when a computer tries to access data in SDRAM. SDRAM latency is often measured in memory bus clock cycles. Because a modern CPU is much faster than SDRAM, the CPU has to wait for a relatively long time for a memory access to complete before it can process the data. SDRAM latency contributes to total memory latency, which causes a significant bottleneck for system performance in modern computers.


SDRAM access

Wikipedia:Diagram needed Diagram Needed.svg
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A digital timing diagram of the sequence of signals and events, with the named time intervals marked. Should assume accessing an array in order that spans multiple rows, and note RAM's row size.

SDRAM is notationally organized into a grid like pattern, with "rows" and "columns". The data stored in SDRAM comes in blocks, defined by the coordinates of the row and column of the specific information. The steps for the memory controller to access data in SDRAM follow in order:

  1. First, the SDRAM is in an idle state.
  2. The controller issues the "active" command. It activates a certain row, as indicated by the address lines, in the SDRAM chip for accessing. This command typically takes a few clock cycles.
  3. After the delay, column address and either "read" or "write" command is issued. Typically the read or write command can be repeated every clock cycle for different column addresses (or a burst mode read can be performed). The read data isn't however available until a few clock cycles later, because the memory is pipelined.
  4. When an access is requested to another row, the current row has to be deactivated by issuing the "precharge" command. The precharge command takes a few clock cycles before a new "active" command can be issued.

SDRAM access has four main measurements (quantified in FSB clock cycles) important in defining the SDRAM latency in a given computer (the 't' prefixes are for 'time'):

The number of clock cycles needed to access a certain column of data in SDRAM. CAS latency, or simply CAS, is known as column address strobe latency, sometimes referred to as tCL.
tRCD (RAS to CAS Delay)
The number of clock cycles needed between a row address strobe (RAS) and a CAS. It is the time required between the computer defining the row and column of the given memory block and the actual read or write to that location. tRCD stands for row address to column address delay.
tRP (RAS Precharge)
The number of clock cycles needed to terminate access to an open row of memory, and open access to the next row. Stands for Row precharge time.
tRAS (Row Active Time)
The minimum number of clock cycles needed to access a certain row of data in RAM between the data request and the precharge command. It's known as active to precharge delay. According to Mushkin, in practice for DDR SDRAM, this should be set to at least tRCD + tCAS + 2 to allow enough time for data to be streamed out. [1]

Pictorially the timings operate as follows:

SDRAM access timing
Row access Column accesses Precharge
tWR (Write)
tCAS (R)
tCAS (R)

Initially, the row address is sent to the DRAM. After tRCD, the row is open and may be accessed. Because this is an SDRAM, multiple column access can be in progress at once. Each read takes time tCAS. When we are done accessing the column, we precharge the SDRAM, which returns us to the starting state after time tRP.

Two other time limits that must also be maintained are tRAS, the time for the refresh of the row to complete before it may be closed again, and tWR, the time that must elapse after the last write before the row may be closed.


As with almost all latency measurement, lower latency results in better performance. RAM speeds are given by the four numbers above, in the format "tCAS-tRCD-tRP-tRAS". So, for example, latency values given as 2.5-3-3-8 would indicate tCAS=2.5, tRCD=3, tRP=3, tRAS=8. (Note that 0.5 values of latency (such as 2.5) are only possible in Double data rate RAM, where two parts of each clock cycle are used)

Most computer users don't need to worry about setting the SDRAM latency because the computer can handle the auto-adjustment to RAM timing based on the Serial Presence Detect (SPD) ROM inside the RAM packaging that defines the four timing values, decided by the RAM manufacturer. Although the SDRAM latency timing can often be adjusted manually, using lower latency settings than the module's rating (overclocking) may cause a computer to crash or fail to boot.

See also

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