|Former type||defunct Public company last listed on NASDAQ|
|Fate||Acquired by Novafora|
|Headquarters||Santa Clara, California, USA|
|Key people||Murray A. Goldman, David Ditzel, Colin Hunter|
|Industry||Intellectual property licensing|
|Revenue||$48.55 million (2006)|
|Operating income||–$25.59 million (2006)|
|Net income||–$23.49 million (2006)|
Transmeta Corporation was a US-based corporation that licensed low power semiconductor intellectual property. Transmeta originally produced very long instruction word code morphing (microcoded) microprocessors, with a focus on reducing power consumption in electronic devices. It was founded in 1995 by Bob Cmelik, Dave Ditzel , Colin Hunter, Ed Kelly, Doug Laird, Malcolm Wing, and Greg Zyner. In January 2009, Transmeta was acquired by Novafora, which ceased operations in August 2009.
Transmeta has produced two x86-compatible CPU architectures: Crusoe and Efficeon. These CPUs have appeared in subnotebooks, blade servers, tablet PCs, a personal cluster computer, and a silent desktop, where low power consumption and heat dissipation are of primary importance.
Revenue for the third quarter of 2007 was $44 million, which included $43 million of services revenue and $1 million of license revenue for royalty payments.
The company began as a stealth startup. Transmeta attempted to staff the company in secret, although speculation online was not uncommon. One source of speculation was the company's bare-bones webpage. On November 12, 1999, a cryptic comment in the HTML appeared:
Yes, there is a secret message, and this is it: Transmeta's policy has been to remain silent about its plans until it had something to demonstrate to the world. On January 19th, 2000, Transmeta is going to announce and demonstrate what Crusoe processors can do. Simultaneously, all of the details will go up on this Web site for everyone on the Internet to see. Crusoe will be cool hardware and software for mobile applications. Crusoe will be unconventional, which is why we wanted to let you know in advance to come look at the entire Web site in January, so that you can get the full story and have access to all of the real details as soon as they are available.
Throughout Transmeta's first few years, little was known about exactly what it would be offering. Its web site went online in mid-1997, and for approximately two and a half years displayed nothing but the text "This web page is not yet here." Information gradually came out of the company, suggesting of a very long instruction word-based (VLIW) design that translated x86 code into its own native code.
In fact, Transmeta marketed their microprocessor technology as extraordinarily innovative and revolutionary in the low-power market segment. They had hoped to be both power and performance leaders in the x86 space. But initial reviews of the Crusoe indicated the performance fell significantly short of projections. Also, during Crusoe development Intel and AMD significantly ramped up speeds and began to address increasing concerns about power consumption. So Crusoe was rapidly cornered into a low-volume, small form factor (SFF), low-power segment of the market.
In response, Transmeta quickly redesigned its technology, and produced the Efficeon processor. The Efficeon was claimed to have twice the performance of the original Crusoe CPU at the same frequency. But the performance was still weak relative to the competition, and the complexity of the chip had increased significantly. This greater size and power consumption may have diluted a key market advantage Transmeta's chips had previously enjoyed over the competition.
Transmeta has employed a number of industry luminaries such as Linus Torvalds and Dave D. Taylor. Initially, its purpose was kept secret, but partially because it had such talent amongst its staff, the industry was constantly abuzz with rumors in addition to 'conspiracy theories' resulting in excellent press relations (PR).
Torvalds left Transmeta in June 2003 to dedicate himself to the further development of the Linux kernel.
As an example of technology media hype, the company was once named as the Most important company in Silicon Valley in an Upside magazine editorial. Less well reported was that the company was never profitable while it was a chip vendor. In 2002, it had a loss of $114 million dollars, in 2003 a loss of $88 million, in 2004 a loss of $107 million.
As of January 2005 the company announced a strategic restructuring away from being a chip product company to an intellectual property company. That is, instead of selling chips, it will sell technology for use by other chip makers. In February 2005, there was wild speculation that AMD might buy Transmeta. In March 2005 Transmeta announced that it was laying off 68 people, leaving 208 employees. About half of the remaining employees were to work on propagating the LongRun2 power optimization technology within Sony products. Sony was reported to be a key licensee of this Transmeta technology.
After its founding in 1995, Transmeta and its goals remained largely unknown until its corporate launch on January 19, 2000. After their initial public offering at the price of $21/share, the value skyrocketed to $46/share. This made Transmeta the last of the great high tech IPOs of the dot-com bubble, not surpassed again until Google’s IPO in 2004. However, Transmeta made their first round of layoffs in June 2002, reducing the headcount of the company by 40%. On May 31, 2005, Transmeta announce the signing of asset purchase and license agreements with Hong Kong’s Culture.com Technology Limited. However, the deal fell apart due to delays in obtaining technology export licenses from the US Department of Commerce, and the parties announced the termination of the agreements on February 9, 2006. On August 10, 2005, Transmeta announced its first-ever profitable quarter. This was followed in 2006 by GameSpot’s report on March 20 that Transmeta was working on an “unnamed” Microsoft project. As it turned out, this was a secure platform under the AMD brand for Microsoft’s FlexGo program. On February 7, 2007, Transmeta closed its engineering services division, terminating 75 employees in the process. This was concurrent with an announcement that the company would no longer develop and sell hardware, but would focus on the development and licensing of intellectual property. Following this, AMD invested $7.5 million in Transmeta, planning to use the company’s patent portfolio in energy-efficient technologies. On August 8, 2008, Transmeta announce that it had licensed its LongRun and low-power chip technologies to Nvidia for a one-time license fee of $25 million. Later in the year, on November 17, Transmeta announced the signing of a definitive agreement to be acquired by Novafora, a digital video processor company based in San Diego, CA, for $255.6 million in cash, subject to adjustments dependent on working capital. The deal was finalized on January 28, 2009, when Novafora announced the completion of its acquisition of Transmeta.
Novafora collapsed in late July, 2009.
On October 11, 2006, Transmeta announced that they had filed a lawsuit against Intel Corporation for infringement of ten Transmeta U.S. patents covering computer architecture and power efficiency technologies.
The complaint charged that Intel had infringed and was infringing Transmeta's patents by making and selling a variety of microprocessor products, including at least Intel's Pentium III, Pentium 4, Pentium M, Core and Core 2 product line.
On October 24, 2007, Transmeta announced an agreement to settle its lawsuit against Intel Corporation. Intel agreed to pay $150 million upfront and $20 million per year for five years to Transmeta in addition to dropping its counter-claims against Transmeta. Transmeta also agreed to license several of its patents and assign a small portfolio of patents to Intel as part of the deal.
The actual Transmeta processors are in-order very long instruction word (VLIW) cores. To execute x86 code, a pure software-based instruction translator dynamically compiles or emulates x86 code sequences, using execution-hotspot guided heuristics. While similar technologies existed (Wabi for Solaris and Linux, FX!32 for Alpha and IA-32 EL for Itanium, open-source DAISY, the Mac 68K emulator for the PowerPC) in the 1990s, the Transmeta approach has set a much higher bar for compatibility—able to execute all x86 instructions from initial boot up to the latest multimedia instructions—while retaining most of its core performance.
Transmeta trademarked the term "code-morphing" to describe their technology.
The operation of Transmeta's code-morphing systems software is very similar to the final optimisation pass of a conventional compiler. Considering a fragment of 32-bit x86 code:
addl %eax,(%esp) // load data from stack, add to %eax addl %ebx,(%esp) // ditto, for %ebx movl %esi,(%ebp) // load %esi from memory subl %ecx,5 // subtract 5 from %ecx register
This is first converted simplistically into native instructions:
ld %r30,[%esp] // load from stack, into temporary add.c %eax,%eax,%r30 // add to %eax, set condition codes. ld %r31,[%esp] add.c %ebx,%ebx,%r31 ld %esi,[%ebp] sub.c %ecx,%ecx,5
The optimiser then eliminates common subexpressions and unnecessary condition code operations and, potentially, applies other optimisations such as loop unrolling:
ld %r30,[%esp] // load from stack only once add %eax,%eax,%r30 add %ebx,%ebx,%r30 // reuse data loaded earlier ld %esi,[%ebp] sub.c %ecx,%ecx,5 // only this last condition code needed
Finally, the optimiser groups individual instructions ("atoms") into VLIW opcodes ("molecules") for the underlying hardware:
ld %r30,[%esp]; sub.c %ecx,%ecx,5 ld %esi,[%ebp]; add %eax,%eax,%r30; add %ebx,%ebx,%r30
These two VLIW opcodes will be executed in two clock cycles, as opposed to the larger number required for the original code executed on an x86 processor which did not perform complex optimisations in hardware.
Transmeta claims several technical benefits to this approach:
Prior to Crusoe's release, rumors indicated Transmeta was relying on these benefits to develop a hybrid PowerPC and x86 processor. But Transmeta would initially concentrate solely on the extremely low-power x86 market.
The ability to quickly update products without a hardware respin was demonstrated in 2002 with an in-the-field upgrade (a download) to enhance CPU performance of the Crusoe based HP Compaq TC1000 tablet PC. It was used again in 2004 when NX bit and SSE3 support were added to the Efficeon product line without requiring hardware changes. In the field upgrades were rare in practice due to system hardware vendors not wanting to incur additional customer support costs or spend additional money on QA for the potential upgrades or bug fixes to shipped products they had already closed the revenue books on.
Crusoe was the first family of microprocessors from Transmeta, named after the literary character Robinson Crusoe.
Transmeta lost much credibility and endured significant criticism due to the poor initial Crusoe showing with large discrepancies between projections and actuals for both performance and power. Although power consumption was somewhat better than Intel and AMD offerings, the end user experience (i.e. battery life) only showed a marginal overall improvement. First, the Code Morphing Software (CMS) combined with cache architecture artificially inflated comparisons between benchmarks and real-world applications. This is due to the repetitive nature of benchmarks and their small footprints. The CMS software overhead may have actually been a key cause of much lower performance for many real-world applications; the simple VLIW core architecture could not compete on computationally-intensive applications; and the southbridge interface was limited by its low bandwidth for graphics or other I/O-intensive applications. Some standard benchmarks even failed to run, throwing the claim of full x86 compatibility into doubt.
The Efficeon processor was Transmeta's second-generation 256-bit VLIW processor design. Like the Crusoe (a 128-bit VLIW architecture), Efficeon stressed computational efficiency, low power consumption, and a low thermal footprint.
A 2004-model 1.6-GHz Transmeta Efficeon (manufactured using a 90-nm process) had roughly the same performance and power characteristics as a 1.6-GHz Intel Atom from 2008 (manufactured using a 45-nm process). The Efficeon included an integrated Northbridge, while the Atom requires an external Northbridge chip (reducing much of the Atom's power consumption benefits).
In principle, it should be possible to optimise x86 code to favour code-morphing software, or even for compilers to target the native VLIW architecture directly. However, Linus Torvalds apparently dismissed these approaches as unrealistic:
The native crusoe code - even if it was documented and available - is not very conducive to general-purpose OS stuff. It has no notion of memory protection, and there's no MMU for code accesses, so things like kernel modules simply wouldn't work.
The translations are usually _better_ than statically compiled native code (because the whole CPU is designed for speculation, and the static compilers don't know how to do that), and thus going to native mode is not necessarily a performance improvement.
So no, it wouldn't really benefit from it, not to mention that it's not even an option since Transmeta has never released enough details to do it anyway. Largely for simple security concerns - if you start giving interfaces for mucking around with the "microcode", you could do some really nasty things.
[…I meant…] "you _cannot_ do that". And we won't even tell the details of _how_ you cannot do that.
In fact, even inside transmeta you cannot do that, without having a specially blessed version of the flash that allows upgrades. If you ever see a machine with a prominent notice saying "CMS upgraded to development version", then that's a hint that it's a machine that TMTA developers could change.—Linus Torvalds , linux-kernel mailing list
In conjunction with its code-morphing software the Efficeon most closely mirrors the feature set of Intel Pentium 4 processors, although, like AMD Opteron processors, it supports a fully integrated memory controller, a HyperTransport IO bus, and the NX bit, or no-execute x86 extension to PAE mode. NX bit support is available starting with CMS version 6.0.4.
Efficeon's computational performance relative to mobile CPUs like the Intel Pentium M is thought to be lower, although little appears to be published about the relative performance of these competing processors.
Efficeon came in two package types: a 783- and a 592-contact ball grid array. Its power consumption was moderate (with some consuming as little as 3 watts at 1 GHz and 7 watts at 1.5 GHz), so it could be passively cooled.
Two generations of this chip were produced. The first generation (TM8600) was manufactured using a TSMC 130 nm process and produced at speeds up to 1.1 GHz. The second generation (TM8800 and TM8820) was manufactured using a Fujitsu 90 nm process and produced at speeds ranging from 1 GHz to 1.7 GHz.
Internally, the Efficeon had two arithmetic logic units, two load/store/add units, two execute units, two floating-point/MMX/SSE/SSE2 units, one branch prediction unit, one alias unit, and one control unit. The VLIW core could execute a 256-bit VLIW instruction per cycle. A VLIW is called a molecule and has room to store eight 32-bit instructions (called atoms) per cycle.
The Efficeon had a 128-KB L1 instruction cache, a 64-KB L1 data cache and a 1-MB L2 cache. All caches were on die.
Additionally the Efficeon CMS (code morphing software) reserved a small portion of main memory (typically 32 MB) for its translation cache of dynamically translated x86 instructions.
The Efficeon processor addressed many of Crusoe's shortcomings and showed roughly a 2x real-world improvement over Crusoe. Its die was considerably smaller than Pentium 4 and Pentium M, when compared in the same process technology. Efficeon's die fabricated in 90 nm is 68 mm², which is 60% of the Pentium 4 in 90 nm, at 112 mm², with both processors possessing a 1 MB L2 cache.
The notion of selling a product into a specific thermal envelope was typically not understood by the mass of reviewers, who tended to compare Efficeon to the gamut of x86 microprocessors, regardless of power consumption or application. One such example of this criticism suggests the performance still significantly lagged Intel's Pentium M (Banias) and AMD's Mobile Athlon XP.
For the 7 to 12 watt thermal envelope in which Efficeon was designed to compete, there are unsubstantiated claims that its frequency far exceeded anything else in the market, at 1.5 GHz and 7 W, while the Centrino at the time could only operate within the 7-W envelope when its frequency was reduced to 1.1 GHz. This claim also admittedly considers only CPU frequency and ignores other significant factors in overall performance, such as core cycles per instruction (CPI), or memory performance and bandwidth, which have varying impact on different benchmarks and system configurations.