# Encyclopedia

(Redirected to x86 article)

Designer Intel 64-bit (16 → 32 → 64) 1978 CISC Register-Memory Variable (1 to 16 bytes) Condition code Little 4 KiB x87, IA-32, P6, MMX, SSE, SSE2, x86-64, SSE3, SSSE3, SSE4, SSE5, AVX yes .16 bit: 6 semi-dedicated registers + bp and sp; 32 bit: 6 GPRs + bp and sp; 64 bit: 14 GPRs + bp and sp.^ Solaris x86 32 bit and 64 bit . What are the system requirements for Java 6? 11 January 2010 15:55 UTC java.com [Source type: FILTERED WITH BAYES] ^ I install the 64 or the 32 bit? X86 — Blogs, Pictures, and more on WordPress 11 January 2010 15:55 UTC en.wordpress.com [Source type: General] ^ Host 64-bit Target 32/64-bit . x86 Open64 Compiler Suite | AMD Developer Central 11 January 2010 15:55 UTC developer.amd.com [Source type: Reference]
The Intel 8086.
Intel Core 2 Duo, an example of an x86-compatible and multi-core 64-bit processor.
AMD Athlon (early version), another technically different, but fully compatible x86 implementation.
.The term x86 refers to a family of instruction set architectures[1] based on the Intel 8086.^ The term x86 actually signifies backward compatibility with the original 8086 instruction set.
• Why is 32bit called x86 and not x32? - PC World Forums 11 January 2010 15:55 UTC forums.pcworld.com [Source type: General]

^ The original x86 CPU was the Intel 8086.
• Why is 32bit called x86 and not x32? - PC World Forums 11 January 2010 15:55 UTC forums.pcworld.com [Source type: General]

^ The instruction set was designed and patented by Intel.
• Plausible: Nvidia Working on x86 CPU - Tom's Hardware 11 January 2010 15:55 UTC www.tomshardware.com [Source type: General]

.The term is derived from the fact that many early processors that are backward compatible with the 8086 also had names ending in "86". Many additions and extensions have been added to the x86 instruction set over the years, almost consistently with full backwards compatibility.^ Pentium MMX - Added the MMX instruction set to the Pentium Classic processor.
• x86@Everything2.com 11 January 2010 15:55 UTC www.everything2.com [Source type: FILTERED WITH BAYES]

^ Nvidia: Expect x86 Processor in 2-3 Years .
• Intel to AMD: Your x86 License Expires in 60 Days - Tom's Hardware 11 January 2010 15:55 UTC www.tomshardware.com [Source type: General]

^ With many instruction sets, hand coding at this level is not too difficult, and ends up being quite efficient.
• x86-64: The Golden Handcuffs 11 January 2010 15:55 UTC www.devhardware.com [Source type: General]

[2] .The architecture has been implemented in processors from Intel, Cyrix, AMD, VIA, and many others.^ Gentoo Embedded is simply embedded Gentoo for the x86 architecture (think Intel, AMD, and Via processors).
• Gentoo Linux Documentation-- Gentoo Embedded x86 Guide 11 January 2010 15:55 UTC www.bulah.com [Source type: General]

^ Summary: The Gentoo Linux x86 Development Project is devoted to keeping Gentoo Linux in good shape on the x86 architecture, which represents all 32-bit Intel-compatible processors .
• Gentoo Linux Projects-- Gentoo Linux x86 Architecture Development 11 January 2010 15:55 UTC www.gentoo.org [Source type: FILTERED WITH BAYES]

^ When AMD first introduced the AMD Opteron processor with Direct Connect Architecture in 2003, the target market was for Read more .
• x86 Articles, Videos, Photos and Opinions | silicon.com 11 January 2010 15:55 UTC www.silicon.com [Source type: General]

.As the x86 term became common after the introduction of the 80386, it usually implies binary compatibility with the 32-bit instruction set of the 80386. This may sometimes be emphasized as x86-32 to distinguish it either from the original 16-bit x86-16 or from the newer 64-bit x86-64 (also called x64).^ Solaris x86 32 bit and 64 bit .
• What are the system requirements for Java 6? 11 January 2010 15:55 UTC java.com [Source type: FILTERED WITH BAYES]

^ Solaris x86 32-bit .
• What are the system requirements for Java 6? 11 January 2010 15:55 UTC java.com [Source type: FILTERED WITH BAYES]

^ Solaris x86 64-bit .
• What are the system requirements for Java 6? 11 January 2010 15:55 UTC java.com [Source type: FILTERED WITH BAYES]

[3] .Although most x86 processors used in new personal computers and servers have 64-bit capabilities, to avoid compatibility problems with older computers or systems, the terms x86-64 and x64 are often used to denote 64-bit software, with the term x86 implying only 32-bit.^ OS, x86 is for x86 systems and a 32 bit processor.
• Re: x86 or x64? - Vista User Access Control - Norton Community 11 January 2010 15:55 UTC community.norton.com [Source type: FILTERED WITH BAYES]

^ I have a x64 processor and a 32 bit OS, so I will have to use the x86 version on my computer because of the OS. .
• Re: x86 or x64? - Vista User Access Control - Norton Community 11 January 2010 15:55 UTC community.norton.com [Source type: FILTERED WITH BAYES]

^ And not all 32-bit processors are x86.
• Why is 32bit called x86 and not x32? - PC World Forums 11 January 2010 15:55 UTC forums.pcworld.com [Source type: General]

[4][5]
.Today, the x86 architecture is ubiquitous among desktop and notebook computers, as well as a growing majority among servers and workstations.^ It was supposed obe a server architecture, a workstation architecture, and eventually a desktop/mobile architecture.
• AnandTech 11 January 2010 15:55 UTC www.anandtech.com [Source type: FILTERED WITH BAYES]

^ Having now defeated all competition in the personal computer market, x86 is now moving up to challenge SPARC and Itanium in large-scale server, and also down to challenge the ubiquitous ARM microcontroller s in the embedded device market.
• x86@Everything2.com 11 January 2010 15:55 UTC www.everything2.com [Source type: FILTERED WITH BAYES]

^ AMD is developing multi-core processors for servers and high-end workstations, and Intel recently moved up plans to ship dual-core processors for its server and desktop systems.
• Rebirth for the x86 - Network World 11 January 2010 15:55 UTC www.networkworld.com [Source type: General]

.A large amount of software supports the platform, including OSes such as MS-DOS, Windows, Linux, BSD, Solaris, and Mac OS X.^ Solaris 9 OS, x86 Platform Edition .
• Technical Case Study: Porting Apache Web Server on Solaris OS From SPARC Platforms to x86 Platforms 11 January 2010 15:55 UTC developers.sun.com [Source type: Reference]

^ With this new push for Solaris x86 I decided to take a fresh look with Sun's latest, Solaris 9 x86 Platform Edition and pit it against Red Hat Linux 9 in a number of categories, including features, security, and performance.
• Sun Versus Linux: The x86 Smack-down 11 January 2010 15:55 UTC www.osnews.com [Source type: General]

^ This paper describes that SUSE Linux Enterprise Server (version 9 in particular) is the most competitive of the Linux operating systems in terms of challenging RISC/UNIX platforms such as Solaris 10 and Windows in performance benchmarks.
• SUSE Linux Enterprise Server 9 and Solaris 10 on x86 - TechWeb Digital Library 11 January 2010 15:55 UTC www.informationweek.com [Source type: General]

.The architecture is relatively uncommon in embedded systems, and low-cost microprocessors markets such as home appliances and toys lack any significant x86 presence.^ It's main purpose is for embedded SBCs (single board computers) based on the x86 architecture were a small non-volatile (flash, compact flash, DiskOnChip) footprint is needed (as low as 10 MB).
• Gentoo Linux Documentation-- Gentoo Embedded x86 Guide 11 January 2010 15:55 UTC www.bulah.com [Source type: General]

^ Even some markets that had seemed locked up by competitors, such as Apple's use of Motorola PowerPCs in the Macintosh computer, have yielded to x86 in recent years.
• Happy birthday, x86! An industry standard turns 30 11 January 2010 15:55 UTC www.computerworld.com [Source type: News]

^ Many have turned to server farms, clusters, or grids of x86 industry-standard servers as cost-effective alternatives to larger, proprietary symmetrical multiprocessing systems.
• x86 server Resources | ZDNet 11 January 2010 15:55 UTC updates.zdnet.com [Source type: General]

[6] .Simpler 16-bit x86 chips are more common here, but AMD's Geode and the new Intel Atom are examples of 32- and 64-bit designs used in this segment.^ AMD used a similar approach to the development of the 64-bit architecture.
• A Glance at the Future: AMD Hammer Processors and x86-64 Technology - X-bit labs 11 January 2010 15:55 UTC www.xbitlabs.com [Source type: FILTERED WITH BAYES]

^ The exact names would be x86-16 , x86-32 and x86-64(or x64) for the x86 chips.
• Why is 32bit called x86 and not x32? - PC World Forums 11 January 2010 15:55 UTC forums.pcworld.com [Source type: General]

^ Intel and AMD produce the majority of the 32-bit chips.
• Will Sun's x86 Gamble Payoff? - InternetNews.com 11 January 2010 15:55 UTC www.internetnews.com [Source type: News]

.Contrary to some popular belief, x86 is not synonymous with IBM PC compatibility as this implies a multitude of other hardware, although some of this is standardized.^ If we were all using Linux, the x86 would not be such an issue and then nVidia would be free to JUST CREATE SOME SUPER AWESOME HARDWARE and not worry about old x86 compatibility.
• Plausible: Nvidia Working on x86 CPU - Tom's Hardware 11 January 2010 15:55 UTC www.tomshardware.com [Source type: General]

^ Overall, the focus on backwards compatibility in both hardware and software has allowed x86 to become the standard architecture that it has.
• x86@Everything2.com 11 January 2010 15:55 UTC www.everything2.com [Source type: FILTERED WITH BAYES]

^ However, keep in mind that with the Solaris for x86 software, the "Sparc, Ultra, or Enterprise System" hardware description would be replaced with "Intel PC".
• Installing Sun Solaris Intel 9 UNIX For x86 PC Installation 11 January 2010 15:55 UTC www.parkansky.com [Source type: General]

.For instance, the original Xbox was designed around an x86 processor, but DRM restrictions led to software requirements that made it incapable of running code that was standard on IBM PC compatible systems.^ As long as the processor is compatible to Intel x86/88 standards, it is supported.
• Turbo-Locator - Locator for x86, V25, Am186, Am188, EX386, EX486, V50, V40, SC400, ... x86, EX, 286, 386, 486compible CPU's using Output of Turbo/Borland Pascal, Borland C++, TASM - Freedemo download 11 January 2010 15:55 UTC www.xellsoft.com [Source type: Reference]

^ Glossary of PC Processors by x86.org .
• PC Processors Guide by x86.org 11 January 2010 15:55 UTC www.rcollins.org [Source type: FILTERED WITH BAYES]

^ PC Processors Guide by x86.org .
• PC Processors Guide by x86.org 11 January 2010 15:55 UTC www.rcollins.org [Source type: FILTERED WITH BAYES]

.Also, the GRID Compass laptop (one of the first on the market), and many others, used x86 chips before the IBM PC compatible market even started.^ Systems based on Motorola's 68020 32 bit processor got a head start in the market because they were binary compatible with the 16 bit 68000 - which already had a bigger memory addressing range than the Intel chips at the time.
• Surviving the Solaris x86 Wars - article in the SPARC ProductDirectory 11 January 2010 15:55 UTC www.sparcproductdirectory.com [Source type: General]

^ Many have turned to server farms, clusters, or grids of x86 industry-standard servers as cost-effective alternatives to larger, proprietary symmetrical multiprocessing systems.
• x86 server Resources | ZDNet 11 January 2010 15:55 UTC updates.zdnet.com [Source type: General]

^ And then the 16-bit Intel 8088 (1979) became the CPU for the first IBM PC. Subsequent generations became new CPUs for IBM PCs and their clones.
• CSCI 350: Operating systems 11 January 2010 15:55 UTC ozark.hendrix.edu [Source type: Reference]

## Chronology

.The table below lists brands of common[7] consumer targeted processors implementing the x86 instruction set, grouped by generations that highlight important points in x86 history.^ Logical instructions The next set of instructions are the logical instructions, listed in Table 4.
• CSCI 350: Operating systems 11 January 2010 15:55 UTC ozark.hendrix.edu [Source type: Reference]

^ Arithmetic instructions The first set of instructions we'll examine are the arithmetic instructions, listed in Table 1.
• CSCI 350: Operating systems 11 January 2010 15:55 UTC ozark.hendrix.edu [Source type: Reference]

^ The general-purpose x86 architecture, with its relatively complex instruction set, has to drag around a lot of transistors and microcode that have only limited utility for many types of computing, including high performance computing.
• HPCwire: The x86 Dynasty 11 January 2010 15:55 UTC www.hpcwire.com [Source type: General]

.Note: CPU generations are not strict: each generation is roughly marked by significantly improved or commercially successful processor microarchitecture designs.^ Together with improved performance at lower clock speeds and improved cache efficiency, the Core architecture brought in a number of energy efficiency optimizations which have proven valuable in keeping the power requirements of successive generations of Core architecture-based CPUs under control.
• Virtualization and multicore x86 CPUs - 8/6/2008 - EDN 11 January 2010 15:55 UTC www.edn.com [Source type: Reference]

^ A processor designed to be binary compatible with i386/i486 and previous generation processors from Intel* Corporation.
• PGI | Support | Glossary 11 January 2010 15:55 UTC www.pgroup.com [Source type: Reference]

^ Taken in total, the number of improved features of the K7 over previous generation processors leaves little doubt that in fact the K7 is truly a 7th generation processor.
• Paul Hsieh's 7th generation x86 CPU Comparisons 11 January 2010 15:55 UTC www.azillionmonkeys.com [Source type: FILTERED WITH BAYES]

Generation First introduced Prominent Consumer CPU brands linear / physical address space Notable (new) features
1 1978 Intel 8086, Intel 8088 16-bit / 20-bit (segmented) first x86 microprocessors
2 1982 Intel 80186, Intel 80188, NEC V20/V30 hardware for fast address calculations, fast mul/div etc
Intel 80286 16-bit (30-bit virtual) / 24-bit (segmented) MMU, for protected mode and a larger address space
3 (IA-32) 1985 Intel386, AMD Am386 32-bit (46-bit virtual) / 32-bit 32-bit instruction set, MMU with paging
4 1989 Intel486, AMD Am486, Cyrix III-Samuel, VIA C3-Samuel2 / VIA C3-Ezra (2001) risc-like pipelining, integrated FPU, on-chip cache
5 1993 Pentium, Pentium MMX superscalar, 64-bit databus, faster FPU, MMX
5/6 1996 Cyrix 6x86, Cyrix MII, Cyrix III-Joshua (2000) register renaming, speculative execution
6 1995 Pentium Pro, AMD K5, Nx586 (1994), Rise mP6 as above / 36-bit physical (PAE) μ-op translation, PAE (Pentium Pro), integrated L2 cache (Pentium Pro), conditional move instructions
1997 AMD K6/-2/3, Pentium II/III, IDT/Centaur-C6 L3-cache support, 3DNow, SSE
7 1999 Athlon, Athlon XP superscalar FPU, wide design (up to three x86 instr./clock)
2000 Pentium 4 deeply pipelined, high frequency, SSE2, hyper-threading
6-M/7-M 2003 Pentium M, Intel Core, VIA C7 (2005) optimized for low power
8 (x86-64) Athlon 64, Opteron 64-bit / 40-bit physical in first AMD implementation. x86-64 instruction set, on-die memory controller, hypertransport
2004 Pentium 4 Prescott very deeply pipelined, very high frequency, SSE3
9 2006 Intel Core 2 low power, multi-core, lower clock frequency, SSE4 (Penryn)
10 2007 AMD Phenom as above / 48-bit physical for AMD Phenom monolithic quad-core, 128 bit FPUs, SSE4a, HyperTransport 3 or QuickPath, modular design
2008 Intel Atom, Intel Core i7 In-order but highly pipelined, very-low-power, native memory controller, on-die L3 cache
VIA Nano Out-of-order, superscalar, hardware-based encryption, very low power, adaptive power management
11 2010 Intel Sandy Bridge, AMD Bulldozer SSE5/AVX, highly modular design

## History

### Background

.The x86 architecture first appeared as the Intel 8086 CPU released in 1978, a fully 16-bit design based on the earlier 8-bit based 8008, 8080 and 8085.^ The 8086 used 16-bit registers.
• CSCI 350: Operating systems 11 January 2010 15:55 UTC ozark.hendrix.edu [Source type: Reference]

^ The 8-bit Intel 8080 (1974) was the CPU for the first successful personal computer, the Altair.
• CSCI 350: Operating systems 11 January 2010 15:55 UTC ozark.hendrix.edu [Source type: Reference]

^ By executing the full set of 8080A/8085 8-bit instructions plus a powerful new set of 16-bit instructions, it enables a system designer familiar with existing 8080 devices to boost performance by a factor of as much as 10 while using essentially the same 8080 software package and development tools.
• PC Processors Guide by x86.org 11 January 2010 15:55 UTC www.rcollins.org [Source type: FILTERED WITH BAYES]

.Although not binary compatible, it was designed to allow assembly language programs written for these processors to be mechanically translated into the equivalent 8086 assembly.^ Versions Real Mode (rm) The 16-bit real-mode (rm) version of smx86 is intended for users who are using 8086, 80186, or equivalent, processors or who do not have large applications and do not need the protection mechanisms of 386-class processors.
• x86 Real Time Kernel Multitasking Embedded Protected Real Mode No Royalty 11 January 2010 15:55 UTC www.smxrtos.com [Source type: Reference]

^ Except as may be expressly permitted in your license agreement for these Programs, no part of these Programs may be reproduced or transmitted in any form or by any means, electronic or mechanical, for any purpose.

^ The instruction streams may be expressed in human-readable assembler mnemonics, which have a literal translation into a binary representation in the digital logic of a particular CPU architecture.
• Virtualization and multicore x86 CPUs - 8/6/2008 - EDN 11 January 2010 15:55 UTC www.edn.com [Source type: Reference]

.This made the new processor a tempting software migration path, but not without significant hardware redesign, which was largely due to the 16-bit external databus.^ Versions Real Mode (rm) The 16-bit real-mode (rm) version of smx86 is intended for users who are using 8086, 80186, or equivalent, processors or who do not have large applications and do not need the protection mechanisms of 386-class processors.
• x86 Real Time Kernel Multitasking Embedded Protected Real Mode No Royalty 11 January 2010 15:55 UTC www.smxrtos.com [Source type: Reference]

^ And then the 16-bit Intel 8088 (1979) became the CPU for the first IBM PC. Subsequent generations became new CPUs for IBM PCs and their clones.
• CSCI 350: Operating systems 11 January 2010 15:55 UTC ozark.hendrix.edu [Source type: Reference]

^ The shock was due to the fact that the only 64-bit processor then was Intel Itanium.
• A Glance at the Future: AMD Hammer Processors and x86-64 Technology - X-bit labs 11 January 2010 15:55 UTC www.xbitlabs.com [Source type: FILTERED WITH BAYES]

To address this, Intel introduced the almost identical 8088, with an 8-bit external databus, which permitted simpler printed circuit boards, demanded fewer (1-bit wide) DRAM chips, and which could be interfaced to already established (i.e. low-cost) 8-bit system and peripheral chips more easily. .Among other, non-technical factors, this contributed to the fact that IBM built their IBM PC around the 8088, despite a presence of 16-bit microprocessors from Motorola, Zilog, and National Semiconductor.^ And then the 16-bit Intel 8088 (1979) became the CPU for the first IBM PC. Subsequent generations became new CPUs for IBM PCs and their clones.
• CSCI 350: Operating systems 11 January 2010 15:55 UTC ozark.hendrix.edu [Source type: Reference]

^ It refers to the fact that the x86 word is 16 bits long, so 32-bit data is two words long.
• CSCI 350: Operating systems 11 January 2010 15:55 UTC ozark.hendrix.edu [Source type: Reference]

^ The 8086 featured a 16-bit data bus, while the 8088 featured an 8-bit data bus.
• PC Processors Guide by x86.org 11 January 2010 15:55 UTC www.rcollins.org [Source type: FILTERED WITH BAYES]

.The IBM PC subsequently took over from Z80-based CP/M systems, Apple IIs, and other popular computers, and became a dominant de-facto standard for personal computers, thus enabling the 8088 and its successors to dominate this large branch of the microprocessor market.^ Capability-based Computer Systems .
• Vx32: Lightweight, User-level Sandboxing on the x86 11 January 2010 15:55 UTC pdos.csail.mit.edu [Source type: Reference]

^ Other markets get similar treatment: the massive mobile phone market has a large number of CPUs tailored for its needs.

^ And then the 16-bit Intel 8088 (1979) became the CPU for the first IBM PC. Subsequent generations became new CPUs for IBM PCs and their clones.
• CSCI 350: Operating systems 11 January 2010 15:55 UTC ozark.hendrix.edu [Source type: Reference]

#### iAPX 432 and the 80286

.Another factor was that the advanced but non-compatible 32-bit Intel 8800 (alias iAPX 432) failed rather miserably in the marketplace around the time the original IBM-PC was launched; the new and fast 80286 actually contributed to the disapointment in the performance of the semi-contemporary 8800 in early 1982. (The 80186, launched in parallel with the 80286, was intended for embedded systems, and would therefore have had a large market anyway.^ Then all we'd be left with would be 32 bit Intel processors.
• Intel to AMD: Your x86 License Expires in 60 Days - Tom's Hardware 11 January 2010 15:55 UTC www.tomshardware.com [Source type: General]

^ There was the iAPX-432 in the 1980s, the i860 in the early 1990s and then Itanium .
• Can the x86 Just Keep Going? - InternetNews.com 11 January 2010 15:55 UTC www.internetnews.com [Source type: General]

^ Systems based on Motorola's 68020 32 bit processor got a head start in the market because they were binary compatible with the 16 bit 68000 - which already had a bigger memory addressing range than the Intel chips at the time.
• Surviving the Solaris x86 Wars - article in the SPARC ProductDirectory 11 January 2010 15:55 UTC www.sparcproductdirectory.com [Source type: General]

) .The market failure of the 32-bit 8800 was a significant impetus for Intel to continue to develop more advanced 8086-compatible processors instead, such as the 80386 (a 32-bit extension of the well performing 80286).^ Then all we'd be left with would be 32 bit Intel processors.
• Intel to AMD: Your x86 License Expires in 60 Days - Tom's Hardware 11 January 2010 15:55 UTC www.tomshardware.com [Source type: General]

^ Intel and AMD have managed to keep x86 fresh by continually adding extensions to the ISA, such as Intel's MMX and SSE instructions in the mid-'90s that improved graphics performance, and AMD's 64-bit extensions this decade that helped bypass the register issue.
• Despite its aging design, the x86 is still in charge - CNET News 11 January 2010 15:55 UTC news.cnet.com [Source type: General]

^ Systems based on Motorola's 68020 32 bit processor got a head start in the market because they were binary compatible with the 16 bit 68000 - which already had a bigger memory addressing range than the Intel chips at the time.
• Surviving the Solaris x86 Wars - article in the SPARC ProductDirectory 11 January 2010 15:55 UTC www.sparcproductdirectory.com [Source type: General]

### Other manufacturers

.At various times, companies such as IBM, NEC[8], AMD, TI, STM, Fujitsu, OKI, Siemens, Cyrix, Intersil, C&T, NexGen, and UMC started to design and/or manufacture x86 processors intended for personal computers as well as embedded systems.^ That's just the design of the computer, has nothing to do with the processor.

^ AMD, Cyrix, IBM, TI, UMC, Siemens, NEC, Harris, and others have all dabbled in the x86 chip industry.
• PC Processors Guide by x86.org 11 January 2010 15:55 UTC www.rcollins.org [Source type: FILTERED WITH BAYES]

^ AMD introduced the K5 processor -- their first in-house x86 design.
• PC Processors Guide by x86.org 11 January 2010 15:55 UTC www.rcollins.org [Source type: FILTERED WITH BAYES]

.Such x86 implementations are seldom plain copies but often employ different internal microarchitectures as well as different solutions at the electronic and physical levels.^ "Every x86 has a different implementation.
• Can the x86 Just Keep Going? - InternetNews.com 11 January 2010 15:55 UTC www.internetnews.com [Source type: General]

^ ARM and X86 are different markets plain and simple.
• DailyTech - VIA Announces 1-Watt x86 CPU 11 January 2010 15:55 UTC www.dailytech.com [Source type: General]

^ The x86-64 has a 64-bit virtual address space, however, initial implementations of the architecture are specified to only use 48 out of these 64 bits, and 40 bits of physical address space.
• Porting NetBSD to the AMD x86-641: a case study in OS portability 11 January 2010 15:55 UTC www.usenix.org [Source type: FILTERED WITH BAYES]
• Porting NetBSD to the AMD x86-641: a case study in OS portability 11 January 2010 15:55 UTC www.usenix.org [Source type: FILTERED WITH BAYES]

.Quite naturally, early compatible chips were 16-bit, while 32-bit designs appeared much later.^ Systems based on Motorola's 68020 32 bit processor got a head start in the market because they were binary compatible with the 16 bit 68000 - which already had a bigger memory addressing range than the Intel chips at the time.
• Surviving the Solaris x86 Wars - article in the SPARC ProductDirectory 11 January 2010 15:55 UTC www.sparcproductdirectory.com [Source type: General]

^ For example, the so-called "Thumb" instruction set extension allows the microcontroller, though 32-bit in nature, to run quite efficiently out of 16-bit memories with about a 25% improvement in code density.
• Migrating from x86 to PowerPC, Part 1: Robots and networked appliances on a shoestring 11 January 2010 15:55 UTC www-106.ibm.com [Source type: General]

^ Since the x86-64 is fully IA32 compatible at power-on, it also needs to deal with getting the CPU out of 16-bit mode, in to 32-bit mode, and this time a couple of steps further, into 64-bit mode.
• Porting NetBSD to the AMD x86-641: a case study in OS portability 11 January 2010 15:55 UTC www.usenix.org [Source type: FILTERED WITH BAYES]
• Porting NetBSD to the AMD x86-641: a case study in OS portability 11 January 2010 15:55 UTC www.usenix.org [Source type: FILTERED WITH BAYES]

.For the personal computer market, real quantities started to appear around 1990 with i386 and i486 compatible processors, often named similarly to Intel's original chips.^ However, Sun chairman and CEO Scott McNealy, who often refers to the IA processors as "Itanic" said there was "just no there, there," when it came to the chips.
• Will Sun's x86 Gamble Payoff? - InternetNews.com 11 January 2010 15:55 UTC www.internetnews.com [Source type: News]

^ Systems based on Motorola's 68020 32 bit processor got a head start in the market because they were binary compatible with the 16 bit 68000 - which already had a bigger memory addressing range than the Intel chips at the time.
• Surviving the Solaris x86 Wars - article in the SPARC ProductDirectory 11 January 2010 15:55 UTC www.sparcproductdirectory.com [Source type: General]

^ Eventually, many embedded processor vendors began manufacturing these chips as a second source to Intel, or in clones of their own.
• PC Processors Guide by x86.org 11 January 2010 15:55 UTC www.rcollins.org [Source type: FILTERED WITH BAYES]

.Other companies, which designed or manufactured x86 or x87 processors, include ITT Corporation, National Semiconductor, ULSI System Technology, and Weitek.^ They have the technology and they can rebuild it for X86 systems.
• Apple using X86 hardware? - AppleInsider 11 January 2010 15:55 UTC forums.appleinsider.com [Source type: FILTERED WITH BAYES]

^ Links to x86 Processor Manufacturers 43.
• x86 Assembly Language FAQ - General Part 1/3 11 January 2010 15:55 UTC www.faqs.org [Source type: Reference]

^ On the other hand, Intel didn't want computer building companies to use CPUs of different architectures than x86 (mostly, Motorola 68K); thereby, Intel licensed manufacturing rights to several semiconductor companies such as AMD, Harris, Hitachi, Siemens, IBM, and probably others.
• x86 CPU Reference (part 1) 11 January 2010 15:55 UTC www.alasir.com [Source type: FILTERED WITH BAYES]

.Following the fully pipelined i486, Intel introduced the Pentium brand name (which, unlike numbers, could be trademarked) for their new line of superscalar x86 designs.^ Intel and Pentium are registered trademarks of Intel Corporation.
• Solaris on Intel - x86 FAQ 11 January 2010 15:55 UTC www.menet.umn.edu [Source type: FILTERED WITH BAYES]

^ Robert Collins' x86.org is a web site devoted to giving you an, uh, alternative but very detailed view of Intel's microprocessor line.
• Guide to x86 Bootstrapping 11 January 2010 15:55 UTC www.nondot.org [Source type: FILTERED WITH BAYES]

^ During the Pentium era, a new Intel competitor emerged.
• PC Processors Guide by x86.org 11 January 2010 15:55 UTC www.rcollins.org [Source type: FILTERED WITH BAYES]

.With the x86 naming scheme now legally cleared, IBM partnered with Cyrix to produce the 5x86 and then the very efficient 6x86 (M1) and 6x86MX (MII) lines of Cyrix designs, which were the first x86 chips implementing register renaming to enable speculative execution.^ IBM started producing Cyrix's chips since September of 1993.
• x86 CPU Reference (part 1) 11 January 2010 15:55 UTC www.alasir.com [Source type: FILTERED WITH BAYES]

^ CUDA and BADABOOM obsolete, and force NVidia to re-design all thier chips to execute x-86 code to run larabee optimized code on Nvidia's future chips, and Nvidia has a very long way to go to catch up to Intel's experience in optimizing compilers for x86 micro-code.
• Plausible: Nvidia Working on x86 CPU - Tom's Hardware 11 January 2010 15:55 UTC www.tomshardware.com [Source type: General]

^ I don't think Intel means to prohibit AMD from making X86 chips, though, especially given that Apple now uses Intel chips.
• Intel to AMD: Your x86 License Expires in 60 Days - Tom's Hardware 11 January 2010 15:55 UTC www.tomshardware.com [Source type: General]

.AMD meanwhile designed and manufactured the advanced but delayed 5k86 (K5), which, internally, was heavily based on AMD's earlier 29K RISC design; similar to NexGen's Nx586, it used a strategy where dedicated pipeline stages decode x86 instructions into uniform and easily handled micro-operations, a method that has remained the basis for most (not all) x86 designs to this day.^ Again, all widely-used x86 operating systems have this capability.
• Vx32: Lightweight, User-level Sandboxing on the x86 11 January 2010 15:55 UTC pdos.csail.mit.edu [Source type: Reference]

^ Decode - the stage where instructions are first decoded from their instruction bytes.
• Paul Hsieh's 7th generation x86 CPU Comparisons 11 January 2010 15:55 UTC www.azillionmonkeys.com [Source type: FILTERED WITH BAYES]

^ AMD introduced the K5 processor -- their first in-house x86 design.
• PC Processors Guide by x86.org 11 January 2010 15:55 UTC www.rcollins.org [Source type: FILTERED WITH BAYES]

Some early versions of these chips had heat dissipation problems. .The 6x86 was also affected by a few minor compatibility issues, the Nx586 lacked an FPU and (the then crucial) pin-compatibility, while the K5 had somewhat disappointing performance when it was (eventually) launched.^ The 6x86 was pin-compatible with the Pentium, though the 6x86 nomenclature might lead the consumer to believe that it is a 6 th -generation (Pentium Pro) compatible chip.
• PC Processors Guide by x86.org 11 January 2010 15:55 UTC www.rcollins.org [Source type: FILTERED WITH BAYES]

.A low customer awareness of alternatives to the Pentium line further contributed to these designs being comparatively unsuccessful, despite the fact that the K5 had very good Pentium compatibility and the 6x86 was significantly faster than the Pentium on integer code.^ Robert Collins' x86.org is a web site devoted to giving you an, uh, alternative but very detailed view of Intel's microprocessor line.
• Guide to x86 Bootstrapping 11 January 2010 15:55 UTC www.nondot.org [Source type: FILTERED WITH BAYES]

^ However, the CPU chips in Sun boxes are RISC chips (Reduced Instruction Set) so they are significantly faster than an Intel chip of a comparable clock speed.
• Installing Sun Solaris Intel 9 UNIX For x86 PC Installation 11 January 2010 15:55 UTC www.parkansky.com [Source type: General]

^ Having CPUs impose these kinds of (reasonable) demands on the software is a very good thing for performance.
• Slashdot Mobile Story | Intel and LG Team Up For x86 Smartphone 11 January 2010 15:55 UTC mobile.slashdot.org [Source type: General]

[9] .AMD later managed to establish itself as a serious contender with the K6 line of processors, which gave way to the highly successful Athlon and Opteron.^ AMD used the Nx686 core and created the successful K6 processor.
• PC Processors Guide by x86.org 11 January 2010 15:55 UTC www.rcollins.org [Source type: FILTERED WITH BAYES]

^ Hardware task-management started with the '386 and continues to this day on chips like the old '486 and Pentium as well as the newer Athlon, Opteron, and Pentium 4 processors.
• Embedded.com - Managing Tasks on x86 Processors 11 January 2010 15:55 UTC www.embedded.com [Source type: FILTERED WITH BAYES]

^ The card has a 300 MHz K6-2 AMD processor and RAM. It emulates hard and floppy drives, serial ports, SuperVGA, mouse, keyboard, etc.
• Solaris on Intel - x86 FAQ 11 January 2010 15:55 UTC www.menet.umn.edu [Source type: FILTERED WITH BAYES]

.There were also other contenders, such as Centaur Technology (formerly IDT), Rise Technology, and Transmeta.^ So there's no telling how long Transmeta might be able to hold onto this advantage until the same technology makes it into conventional x86 architectures.
• Paul Hsieh's 7th generation x86 CPU Comparisons 11 January 2010 15:55 UTC www.azillionmonkeys.com [Source type: FILTERED WITH BAYES]

^ Centaur Technologies (a wholly owned subsidiary of IDT) created a fast, cheap, and somewhat low power Pentium compatible chip.
• PC Processors Guide by x86.org 11 January 2010 15:55 UTC www.rcollins.org [Source type: FILTERED WITH BAYES]

.VIA Technologies' energy efficient C3 and C7 processors, which were designed by Centaur, have been sold for many years, and Centaur newest design, the VIA Nano, is their first processor with superscalar and speculative execution.^ Memory technologies change somewhat more slowly, requiring a new Northbridge design every few years.

^ In the same year almost 3 billion ARM processors were sold.

^ AMD introduced the K5 processor -- their first in-house x86 design.
• PC Processors Guide by x86.org 11 January 2010 15:55 UTC www.rcollins.org [Source type: FILTERED WITH BAYES]

.It was, perhaps interestingly, introduced at about the same time as Intel's first "in-order" processor since the original Pentium, the Intel Atom.^ First, Intel introduced a cache .
• PC Processors Guide by x86.org 11 January 2010 15:55 UTC www.rcollins.org [Source type: FILTERED WITH BAYES]

^ And you thought that the Intel FDIV was the first bug in a processor!
• x86 Assembly Language FAQ - General Part 1/3 11 January 2010 15:55 UTC www.faqs.org [Source type: Reference]

^ At one time, Sun did do a port with Intel's Itanium processors.
• Will Sun's x86 Gamble Payoff? - InternetNews.com 11 January 2010 15:55 UTC www.internetnews.com [Source type: News]

### Extensions of word size

.The instruction set architecture has twice been extended to a larger word size.^ For the PIO case, the instructions remained the same, so no changes were needed, except for some modifications to make it fit the extended 64-bit register set.
• Porting NetBSD to the AMD x86-641: a case study in OS portability 11 January 2010 15:55 UTC www.usenix.org [Source type: FILTERED WITH BAYES]
• Porting NetBSD to the AMD x86-641: a case study in OS portability 11 January 2010 15:55 UTC www.usenix.org [Source type: FILTERED WITH BAYES]

^ Merced is not CISC (Complex Instruction Set Computer), RISC (Reduced Instruction Set Computer), but closely resembles a VLIW design (Very Long Instruction Word).
• PC Processors Guide by x86.org 11 January 2010 15:55 UTC www.rcollins.org [Source type: FILTERED WITH BAYES]

^ Intel continued to extend the instruction set; but more significantly, Intel added four more address lines and a new operating mode called "protected mode."
• PC Processors Guide by x86.org 11 January 2010 15:55 UTC www.rcollins.org [Source type: FILTERED WITH BAYES]

.In 1985, Intel released the 32-bit 80386 (or i386) which gradually replaced the earlier 16-bit chips in computers (although typically not in embedded systems) during the following years; this extended programming model was originally referred to as the i386 architecture (like its first implementation) but Intel later dubbed it IA-32 when introducing its (unrelated) IA-64 architecture.^ Three years later, the 16-bit 8086 made its debut.
• Happy birthday, x86! An industry standard turns 30 11 January 2010 15:55 UTC www.computerworld.com [Source type: News]

^ EiB on all 64-bit architectures .
• Release Notes for SUSE Linux Enterprise Server 11 11 January 2010 15:55 UTC www.novell.com [Source type: FILTERED WITH BAYES]

^ Also like the 80286, the 80386 was not introduced in any computer systems for many years after its introduction.
• PC Processors Guide by x86.org 11 January 2010 15:55 UTC www.rcollins.org [Source type: FILTERED WITH BAYES]

.In 1999-2003, AMD extended this 32-bit architecture to 64 bits and referred to it as x86-64 in early documents and later as AMD64.^ AMD x86-64 architecture programmer’s manual, September 2002.
• Vx32: Lightweight, User-level Sandboxing on the x86 11 January 2010 15:55 UTC pdos.csail.mit.edu [Source type: Reference]

^ The x86-64 architecture is essentially a 64-bit extension of the IA32 architecture.
• Porting NetBSD to the AMD x86-641: a case study in OS portability 11 January 2010 15:55 UTC www.usenix.org [Source type: FILTERED WITH BAYES]
• Porting NetBSD to the AMD x86-641: a case study in OS portability 11 January 2010 15:55 UTC www.usenix.org [Source type: FILTERED WITH BAYES]

^ Vast effort has been invested to modernize the CPU and overall system architecture, but even the current 64-bit architectures are constrained to some degree by legacy considerations.
• Migrating from x86 to PowerPC, Part 1: Robots and networked appliances on a shoestring 11 January 2010 15:55 UTC www-106.ibm.com [Source type: General]

Intel soon adopted AMD's architectural extensions under the name IA-32e which was later renamed EM64T and finally Intel 64. Among these five names, the original x86-64 is probably the most commonly used, although Microsoft and Sun Microsystems also use the term x64.

## Overview

### Basic properties of the architecture

.The x86 architecture is a variable instruction length, primarily two-address "CISC" design with emphasis on backward compatibility.^ "They are changing x86 architecture, but when they do it's always additive and always backwards compatible," Reynolds told InternetNews.com .
• Can the x86 Just Keep Going? - InternetNews.com 11 January 2010 15:55 UTC www.internetnews.com [Source type: General]

^ Real mode refers to an essentially extinct form of backwards compatibility in the x86 architectures, and is sometimes called "16-bit mode".
• Guide to x86 Bootstrapping 11 January 2010 15:55 UTC www.nondot.org [Source type: FILTERED WITH BAYES]

^ But more importantly, as they target better and better process technologies, they can change most aspects of their design without compromising x86 compatibility.
• Paul Hsieh's 7th generation x86 CPU Comparisons 11 January 2010 15:55 UTC www.azillionmonkeys.com [Source type: FILTERED WITH BAYES]

.The instruction set is not typical CISC however, but basically an extended and orthogonalized version of the simple eight-bit 8008, 8080, and 8085 architectures.^ By executing the full set of 8080A/8085 8-bit instructions plus a powerful new set of 16-bit instructions, it enables a system designer familiar with existing 8080 devices to boost performance by a factor of as much as 10 while using essentially the same 8080 software package and development tools.
• PC Processors Guide by x86.org 11 January 2010 15:55 UTC www.rcollins.org [Source type: FILTERED WITH BAYES]

^ However, the CPU chips in Sun boxes are RISC chips (Reduced Instruction Set) so they are significantly faster than an Intel chip of a comparable clock speed.
• Installing Sun Solaris Intel 9 UNIX For x86 PC Installation 11 January 2010 15:55 UTC www.parkansky.com [Source type: General]

^ Renamed registers are typically written back to the real architectural registers when the instruction retires.
• Paul Hsieh's 7th generation x86 CPU Comparisons 11 January 2010 15:55 UTC www.azillionmonkeys.com [Source type: FILTERED WITH BAYES]

.Byte-addressing is supported and words are stored in memory with little-endian byte order.^ That is, code shouldn't depend on structure or union alignments, or in what order a number appears in a word ("big or little endian").
• Solaris on Intel - x86 FAQ 11 January 2010 15:55 UTC www.menet.umn.edu [Source type: FILTERED WITH BAYES]

^ Later CPUs also support an extended version of this scheme called Physical Address Extensions (PAE), enabling the use of more than 4G of physical memory.
• Porting NetBSD to the AMD x86-641: a case study in OS portability 11 January 2010 15:55 UTC www.usenix.org [Source type: FILTERED WITH BAYES]
• Porting NetBSD to the AMD x86-641: a case study in OS portability 11 January 2010 15:55 UTC www.usenix.org [Source type: FILTERED WITH BAYES]

• AnandTech 11 January 2010 15:55 UTC www.anandtech.com [Source type: FILTERED WITH BAYES]

.Memory access to unaligned addresses is allowed for all supported word sizes.^ Later CPUs also support an extended version of this scheme called Physical Address Extensions (PAE), enabling the use of more than 4G of physical memory.
• Porting NetBSD to the AMD x86-641: a case study in OS portability 11 January 2010 15:55 UTC www.usenix.org [Source type: FILTERED WITH BAYES]
• Porting NetBSD to the AMD x86-641: a case study in OS portability 11 January 2010 15:55 UTC www.usenix.org [Source type: FILTERED WITH BAYES]

^ Thus, a normal segment with base b and limit l permits memory accesses at virtual addresses between 0 and l , and maps these virtual addresses to linear addresses from b to b + l .
• Vx32: Lightweight, User-level Sandboxing on the x86 11 January 2010 15:55 UTC pdos.csail.mit.edu [Source type: Reference]

^ As the memory is accessed through the processor in all Hammer systems, it may negatively tell on the GPU performance.
• A Glance at the Future: AMD Hammer Processors and x86-64 Technology - X-bit labs 11 January 2010 15:55 UTC www.xbitlabs.com [Source type: FILTERED WITH BAYES]

.The largest native size for integer arithmetics and memory addresses (or offsets) is 16, 32, or 64 bits depending on architecture generation (newer processors include direct support for smaller integers as well).^ EiB on all 64-bit architectures .
• Release Notes for SUSE Linux Enterprise Server 11 11 January 2010 15:55 UTC www.novell.com [Source type: FILTERED WITH BAYES]

^ Unfortunately, 16-bit memory addresses only support 2 16 bytes (64KB).
• CSCI 350: Operating systems 11 January 2010 15:55 UTC ozark.hendrix.edu [Source type: Reference]

^ The added features include 16-bit arithmetic, signed 8- and 16-bit arithmetic (including multiply and divide), efficient interruptible byte-string operations, and improved bit manipulation.
• PC Processors Guide by x86.org 11 January 2010 15:55 UTC www.rcollins.org [Source type: FILTERED WITH BAYES]

Multiple scalar values can be handled simultaneously via the SIMD unit present in later generations, as described below.[10] .Immediate addressing offsets and immediate data may be expressed as 8-bit quantities for the frequently occurring cases or contexts where a -128..127 range is enough.^ A big change in Solaris 7 is its support for 64-bit virtual addresses on UltraSPARCs, in contrast to 2.6 which has only 64-bit file offsets.
• Solaris on Intel - x86 FAQ 11 January 2010 15:55 UTC www.menet.umn.edu [Source type: FILTERED WITH BAYES]

^ The first argument is the target eip ; the second is the address of the end of the 32-bit jump offset to be patched.
• Vx32: Lightweight, User-level Sandboxing on the x86 11 January 2010 15:55 UTC pdos.csail.mit.edu [Source type: Reference]

^ Shortly after the 80386 was introduced, Intel introduced the 80386 SX. To avoid confusion, Intel renamed the 80386 to the 80386 DX. The SX was a cost-reduced 80386 with a 16-bit data bus, and 24-bit address bus.
• PC Processors Guide by x86.org 11 January 2010 15:55 UTC www.rcollins.org [Source type: FILTERED WITH BAYES]

.Typical instructions are therefore 2 or 3 bytes in length (although some are much longer, and some are single-byte).^ RISC instructions are typically characterized by fix length instruction sets (for example, all instructions are 32-bits each).
• PC Processors Guide by x86.org 11 January 2010 15:55 UTC www.rcollins.org [Source type: FILTERED WITH BAYES]

^ A CISC microprocessor is one in which the number of bytes needed to represent the opcode instruction is not a fixed, regular length (for example, 32-bits each).
• PC Processors Guide by x86.org 11 January 2010 15:55 UTC www.rcollins.org [Source type: FILTERED WITH BAYES]

^ Used to execute single-instruction, multiple-data (SIMD) operations on 64-bit packed byte, 2-byte, and 4-byte integers.
• Mac Dev Center: Mac OS X ABI Function Call Guide: IA-32 Function Calling Conventions 11 January 2010 15:55 UTC developer.apple.com [Source type: Reference]

.To further conserve encoding space, most registers are expressed in opcodes using three bits, and at most one operand to an instruction can be a memory location (some highly orthogonal "CISC" designs, such as the PDP-11, may use two).^ The 8086 used 16-bit registers.
• CSCI 350: Operating systems 11 January 2010 15:55 UTC ozark.hendrix.edu [Source type: Reference]

^ The xchg instruction exchanges the data in two locations, of which one must be a register.
• CSCI 350: Operating systems 11 January 2010 15:55 UTC ozark.hendrix.edu [Source type: Reference]

^ The instructions are translated to Macro-Ops which themselves contain two packaged ops (one being one of: load, load/store, store, and the other being an alu op.
• Paul Hsieh's 7th generation x86 CPU Comparisons 11 January 2010 15:55 UTC www.azillionmonkeys.com [Source type: FILTERED WITH BAYES]

.However, this memory operand may also be the destination (or a combined source and destination), while the other operand, the source, can be either register or immediate.^ (The esi and edi registers are designed for this purpose: The names stand for source index and destination index , respectively.
• CSCI 350: Operating systems 11 January 2010 15:55 UTC ozark.hendrix.edu [Source type: Reference]

^ However the K7 has the opportunity to pull even with SSE in this area as well by virtue of its use, once again, of memory operands.
• Paul Hsieh's 7th generation x86 CPU Comparisons 11 January 2010 15:55 UTC www.azillionmonkeys.com [Source type: FILTERED WITH BAYES]

^ A special 64-bit immediate register move instruction was added to conveniently use 64-bit constants; 64-bit immediate values are not allowed in other instructions.
• Porting NetBSD to the AMD x86-641: a case study in OS portability 11 January 2010 15:55 UTC www.usenix.org [Source type: FILTERED WITH BAYES]
• Porting NetBSD to the AMD x86-641: a case study in OS portability 11 January 2010 15:55 UTC www.usenix.org [Source type: FILTERED WITH BAYES]

.Among other factors, this contributes to a code footprint that rivals eight-bit machines and enables efficient use of instruction cache memory.^ By executing the full set of 8080A/8085 8-bit instructions plus a powerful new set of 16-bit instructions, it enables a system designer familiar with existing 8080 devices to boost performance by a factor of as much as 10 while using essentially the same 8080 software package and development tools.
• PC Processors Guide by x86.org 11 January 2010 15:55 UTC www.rcollins.org [Source type: FILTERED WITH BAYES]

^ For example, the so-called "Thumb" instruction set extension allows the microcontroller, though 32-bit in nature, to run quite efficiently out of 16-bit memories with about a 25% improvement in code density.
• Migrating from x86 to PowerPC, Part 1: Robots and networked appliances on a shoestring 11 January 2010 15:55 UTC www-106.ibm.com [Source type: General]

^ To give you a bit of perspective on Sun hardware, the Sparc, Ultra, and other Sun workstation models are meant to be fast graphics machines.
• Installing Sun Solaris Intel 9 UNIX For x86 PC Installation 11 January 2010 15:55 UTC www.parkansky.com [Source type: General]

.The relatively small number of general registers (also inherited from its 8-bit ancestors) has made register-relative addressing (using small immediate offsets) an important method of accessing operands, especially on the stack.^ The 8086 used 16-bit registers.
• CSCI 350: Operating systems 11 January 2010 15:55 UTC ozark.hendrix.edu [Source type: Reference]

^ So, 64bit mode features the support of: 64bit virtual addresses; 8 new 64bit general-purpose registers; GPRs extension to 64bit (including the "old" EAX, EBX and so on); 64-bitinstruction pointer; New relative instruction pointer (RIP) method of data-addressing; Continuous address space with a single space for instructions, data and the stack.
• A Glance at the Future: AMD Hammer Processors and x86-64 Technology - X-bit labs 11 January 2010 15:55 UTC www.xbitlabs.com [Source type: FILTERED WITH BAYES]

^ In the 8086, a memory address was computed as follows: Take the segment register, shift it left four bits, and add the address to this.
• CSCI 350: Operating systems 11 January 2010 15:55 UTC ozark.hendrix.edu [Source type: Reference]

Much work has therefore been invested in making such accesses as fast as register accesses, i.e. a one cycle instruction throughput, in most circumstances where the accessed data is available in the top-level cache.

#### Floating point and SIMD

.A dedicated floating point processor with 80-bit internal registers, the 8087, was developed for the original 8086.^ Floating-point register .
• Mac Dev Center: Mac OS X ABI Function Call Guide: IA-32 Function Calling Conventions 11 January 2010 15:55 UTC developer.apple.com [Source type: Reference]

^ The 8086 used 16-bit registers.
• CSCI 350: Operating systems 11 January 2010 15:55 UTC ozark.hendrix.edu [Source type: Reference]

^ In the 8086, a memory address was computed as follows: Take the segment register, shift it left four bits, and add the address to this.
• CSCI 350: Operating systems 11 January 2010 15:55 UTC ozark.hendrix.edu [Source type: Reference]

.This chip subsequently developed into the extended 80387, and later processors incorporated a backwards compatible version of this functionality on the same chip as the main processor.^ Leaf's next version will support 32 nodes and up to 64TB of main memory using Intel CPUs compatible with the Intel Quick Path Interconnect (QPI) 1.1 beginning with the promised Sandy Bridge processors.
• 3Leaf Makes x86 Boxes into SMP Cloudware | JAVA Developer's Journal 11 January 2010 15:55 UTC java.sys-con.com [Source type: General]

^ We then load the second and subsequent sectors until we have bootstrapped ourselves into MS-DOS. Some versions of MS-DOS (6.x and up?
• Guide to x86 Bootstrapping 11 January 2010 15:55 UTC www.nondot.org [Source type: FILTERED WITH BAYES]

^ Later CPUs also support an extended version of this scheme called Physical Address Extensions (PAE), enabling the use of more than 4G of physical memory.
• Porting NetBSD to the AMD x86-641: a case study in OS portability 11 January 2010 15:55 UTC www.usenix.org [Source type: FILTERED WITH BAYES]
• Porting NetBSD to the AMD x86-641: a case study in OS portability 11 January 2010 15:55 UTC www.usenix.org [Source type: FILTERED WITH BAYES]

.In addition to this, modern x86 designs also contain a SIMD-unit (see SSE below) where instructions can work in parallel on (one or two) 128-bit words, each containing 2 or 4 floating point numbers (each 64 or 32 bits wide), or, alternatively, 2,4,8 or 16 integers (each 64,32,16 or 8 bits wide).^ It refers to the fact that the x86 word is 16 bits long, so 32-bit data is two words long.
• CSCI 350: Operating systems 11 January 2010 15:55 UTC ozark.hendrix.edu [Source type: Reference]

^ Used to execute 32-bit and 64-bit floating-point arithmetic.
• Mac Dev Center: Mac OS X ABI Function Call Guide: IA-32 Function Calling Conventions 11 January 2010 15:55 UTC developer.apple.com [Source type: Reference]

^ SSE also adds a set of new registers, 64 bits wide, for use with SSE instructions.
• Porting NetBSD to the AMD x86-641: a case study in OS portability 11 January 2010 15:55 UTC www.usenix.org [Source type: FILTERED WITH BAYES]
• Porting NetBSD to the AMD x86-641: a case study in OS portability 11 January 2010 15:55 UTC www.usenix.org [Source type: FILTERED WITH BAYES]

.The wide SIMD registers means that existing x86 processors can load or store up to 128 bits of memory data in a single instruction and also perform bitwise operations (although not integer arithmetics[11]) on full 128-bits quantities in parallel.^ Used to execute single-instruction, multiple-data (SIMD) operations on 64-bit packed byte, 2-byte, and 4-byte integers.
• Mac Dev Center: Mac OS X ABI Function Call Guide: IA-32 Function Calling Conventions 11 January 2010 15:55 UTC developer.apple.com [Source type: Reference]

^ By executing the full set of 8080A/8085 8-bit instructions plus a powerful new set of 16-bit instructions, it enables a system designer familiar with existing 8080 devices to boost performance by a factor of as much as 10 while using essentially the same 8080 software package and development tools.
• PC Processors Guide by x86.org 11 January 2010 15:55 UTC www.rcollins.org [Source type: FILTERED WITH BAYES]

^ The added features include 16-bit arithmetic, signed 8- and 16-bit arithmetic (including multiply and divide), efficient interruptible byte-string operations, and improved bit manipulation.
• PC Processors Guide by x86.org 11 January 2010 15:55 UTC www.rcollins.org [Source type: FILTERED WITH BAYES]

.Planned x86 processors will have 256-bit SIMD operations (including 256-bit memory load and store).^ The added features include 16-bit arithmetic, signed 8- and 16-bit arithmetic (including multiply and divide), efficient interruptible byte-string operations, and improved bit manipulation.
• PC Processors Guide by x86.org 11 January 2010 15:55 UTC www.rcollins.org [Source type: FILTERED WITH BAYES]

^ From the Pentium III and up, Streaming SIMD Extensions (SSE), a class of instructions dealing with parallelized load/store and computation, targeted at graphics applications.
• Porting NetBSD to the AMD x86-641: a case study in OS portability 11 January 2010 15:55 UTC www.usenix.org [Source type: FILTERED WITH BAYES]
• Porting NetBSD to the AMD x86-641: a case study in OS portability 11 January 2010 15:55 UTC www.usenix.org [Source type: FILTERED WITH BAYES]

^ Vx32 performance is independent of the host operating system’s choice of processor mode, because vx32 always runs guest code in 32-bit mode.
• Vx32: Lightweight, User-level Sandboxing on the x86 11 January 2010 15:55 UTC pdos.csail.mit.edu [Source type: Reference]

### Current implementations

.During execution, current x86 processors employ a few extra decoding steps to split most instructions into smaller pieces (micro-operations).^ In order not to lose too much of the performance with the addition of extra pipeline stages, AMD subdivided the process of the instructions fetch from the cache and the instruction decoding into Macro-ops (simple operations performed by the processor core).
• A Glance at the Future: AMD Hammer Processors and x86-64 Technology - X-bit labs 11 January 2010 15:55 UTC www.xbitlabs.com [Source type: FILTERED WITH BAYES]

^ In the x86 architecture, segmentation is an address translation step that the processor applies immediately before page translation.
• Vx32: Lightweight, User-level Sandboxing on the x86 11 January 2010 15:55 UTC pdos.csail.mit.edu [Source type: Reference]

^ I.e, move the decoding of old hat instructions into software and re-organise the instruction set.
• AnandTech 11 January 2010 15:55 UTC www.anandtech.com [Source type: FILTERED WITH BAYES]

.These are then handed to a control unit that buffers and schedules them in compliance with x86-semantics so that they can be executed, partly in parallel, by one of several (more or less specialized) execution units.^ These renderers have been recently supplanted by graphics processing units (GPUs), which first took over fixed-function operations such as tria  more...
• Larrabee 11 January 2010 15:55 UTC portal.acm.org [Source type: Academic]

^ Charters For comp.lang.asm.x86 and alt.lang.asm Newsgroups To know whether or not these newsgroups will meet your needs, the purpose for which they were created are given below.
• x86 Assembly Language FAQ - General Part 1/3 11 January 2010 15:55 UTC www.faqs.org [Source type: Reference]

^ They are a form of security domain, not unlike the access control methods for pages or segments on processors with a full memory management unit.
• AnandTech 11 January 2010 15:55 UTC www.anandtech.com [Source type: FILTERED WITH BAYES]

.These modern x86 designs are thus superscalar, and also capable of out of order and speculative execution (via register renaming), which means they may execute multiple (partial or complete) x86 instructions simultaneously, and not necessarily in the same order as given in the instruction stream.^ Charters For comp.lang.asm.x86 and alt.lang.asm Newsgroups To know whether or not these newsgroups will meet your needs, the purpose for which they were created are given below.
• x86 Assembly Language FAQ - General Part 1/3 11 January 2010 15:55 UTC www.faqs.org [Source type: Reference]

^ Out of order execution - a feature of the Post-RISC architecture whereby instructions may actual complete their calculation steps in an order different from that in which they were issued in the original program.
• Paul Hsieh's 7th generation x86 CPU Comparisons 11 January 2010 15:55 UTC www.azillionmonkeys.com [Source type: FILTERED WITH BAYES]

^ For example, a superscalar architecture aims to issue more than one instruction per clock tick (on average) from a single instruction stream by extracting the nascent parallelism of the stream in order to simultaneously feed multiple execution units.
• Virtualization and multicore x86 CPUs - 8/6/2008 - EDN 11 January 2010 15:55 UTC www.edn.com [Source type: Reference]

.When introduced, this approach was sometimes referred to as a "RISC core" or as "RISC translation", partly for marketing reasons, but also because these micro-operations share some properties with certain types of RISC instructions.^ It uses instruction translation to convert the cumbersome x86 instruction set to high performance RISC-like instructions, and drives those RISC instructions with a state of the art microarchitecture.
• Paul Hsieh's 7th generation x86 CPU Comparisons 11 January 2010 15:55 UTC www.azillionmonkeys.com [Source type: FILTERED WITH BAYES]

^ The reason for these two instructions is that occasionally there is a sequence of instructions that must be executed without interruption.
• CSCI 350: Operating systems 11 January 2010 15:55 UTC ozark.hendrix.edu [Source type: Reference]

^ You can ignore the segment registers most of the time in your assembly programs, though, because the operating system sets them up so that the instructions do the right thing.
• CSCI 350: Operating systems 11 January 2010 15:55 UTC ozark.hendrix.edu [Source type: Reference]

.However, traditional microcode (used since the 1950s) also inherently shares many of the same properties; the new approach differs mainly in that the translation to micro-operations now occurs asynchronously.^ Since the decoder turns x86 into micro-ops, if the i7 detects a loop, then the decoder won't be used until the loop ends.
• Slashdot Mobile Story | Intel and LG Team Up For x86 Smartphone 11 January 2010 15:55 UTC mobile.slashdot.org [Source type: General]

^ These statistics stand in contrast to the lack of willingness to execute anywhere near this many applications on the same machine running a single operating system instance.
• Virtualization and multicore x86 CPUs - 8/6/2008 - EDN 11 January 2010 15:55 UTC www.edn.com [Source type: Reference]

^ But since we are now finally running in long mode, it is within range of the jump instructions, so use one to finally start executing the actual kernel code.
• Porting NetBSD to the AMD x86-641: a case study in OS portability 11 January 2010 15:55 UTC www.usenix.org [Source type: FILTERED WITH BAYES]
• Porting NetBSD to the AMD x86-641: a case study in OS portability 11 January 2010 15:55 UTC www.usenix.org [Source type: FILTERED WITH BAYES]

.Not having to synchronize the execution units with the decode steps opens up possibilities for more analysis of the (buffered) code stream, and therefore permits detection of operations that can be performed in parallel, simultaneously feeding more than one execution unit.^ The macro operation bundles that are decoded are just a convenient structure inside of the K7 which gives much more complete coverage of the x86 instruction set (which have the net effect of delivering more operations to the function units per clock.
• Paul Hsieh's 7th generation x86 CPU Comparisons 11 January 2010 15:55 UTC www.azillionmonkeys.com [Source type: FILTERED WITH BAYES]

^ To restart the add-on module from the desktop, perform these steps: Open the Services settings application from the main menu.
• ReleaseNotes2008.11 (Project indiana.x86) - XWiki 11 January 2010 15:55 UTC hub.opensolaris.org [Source type: Reference]

^ Vx32 performance is independent of the host operating system’s choice of processor mode, because vx32 always runs guest code in 32-bit mode.
• Vx32: Lightweight, User-level Sandboxing on the x86 11 January 2010 15:55 UTC pdos.csail.mit.edu [Source type: Reference]

.The latest processors also do the opposite when appropriate; they combine certain x86 sequences (such as a compare followed by a conditional jump) into a more complex micro-op which fits the execution model better and thus can be executed faster or with less machine resources involved.^ I was going to ask, how can they compete when x86 processors cost an ARM and a leg!
• Slashdot Mobile Story | Intel and LG Team Up For x86 Smartphone 11 January 2010 15:55 UTC mobile.slashdot.org [Source type: General]

^ The thing is that Adobe does create new versions of their software in > > > less time than you state, just that they don't do it for Solaris on x86.
• OpenSolaris Forums : Adobe Acrobat for Solaris x86 ... 11 January 2010 15:55 UTC www.opensolaris.org [Source type: FILTERED WITH BAYES]

^ Since the decoder turns x86 into micro-ops, if the i7 detects a loop, then the decoder won't be used until the loop ends.
• Slashdot Mobile Story | Intel and LG Team Up For x86 Smartphone 11 January 2010 15:55 UTC mobile.slashdot.org [Source type: General]

.Another way to try to improve performance is to cache the decoded micro-operations, so the processor can directly access the decoded micro-operations from a special cache, instead of decoding them again.^ Second, direct processor interconnections solve the problem of cache coherence by transferring the data directly from one CPU to another.
• A Glance at the Future: AMD Hammer Processors and x86-64 Technology - X-bit labs 11 January 2010 15:55 UTC www.xbitlabs.com [Source type: FILTERED WITH BAYES]

^ Chipset vendors began dreaming of ways they could help improve the performance of the computer, thus giving their products a competitive advantage.
• PC Processors Guide by x86.org 11 January 2010 15:55 UTC www.rcollins.org [Source type: FILTERED WITH BAYES]

^ In order not to lose too much of the performance with the addition of extra pipeline stages, AMD subdivided the process of the instructions fetch from the cache and the instruction decoding into Macro-ops (simple operations performed by the processor core).
• A Glance at the Future: AMD Hammer Processors and x86-64 Technology - X-bit labs 11 January 2010 15:55 UTC www.xbitlabs.com [Source type: FILTERED WITH BAYES]

.The Execution Trace Cache found in Intel's NetBurst Microarchitecture (Pentium 4) is so far the only widespread example of this technique.^ This is a particularly hard case for native execution, especially if the processor’s instruction cache uses only the low 12 bits of the instruction address as the cache index.
• Vx32: Lightweight, User-level Sandboxing on the x86 11 January 2010 15:55 UTC pdos.csail.mit.edu [Source type: Reference]

^ Although Intel correctly points out that x86 to micro-op decode penalties no longer affect branch mispredicts, the bulk of the pipeline stages in the architecture appear between the trace cache output and execution stages.
• Paul Hsieh's 7th generation x86 CPU Comparisons 11 January 2010 15:55 UTC www.azillionmonkeys.com [Source type: FILTERED WITH BAYES]

^ This technique has been used, for example, to translate SQL database queries into an intermediate functional programming language whose execution is distributed over an array of execution elements.
• Virtualization and multicore x86 CPUs - 8/6/2008 - EDN 11 January 2010 15:55 UTC www.edn.com [Source type: Reference]

.Transmeta use a completely different method in their x86 compatible CPUs.^ The core chip is not an x86 compatible CPU at all, but rather a VLIW engine.
• Paul Hsieh's 7th generation x86 CPU Comparisons 11 January 2010 15:55 UTC www.azillionmonkeys.com [Source type: FILTERED WITH BAYES]

^ Data movement instructions Table 3 lists the x86 assembly instructions useful for moving data between different areas of the computer.
• CSCI 350: Operating systems 11 January 2010 15:55 UTC ozark.hendrix.edu [Source type: Reference]

^ Back in the day IBM showed a Dual Core 601 / x86 CPU. That's what we could use.
• Amigaworld.net - The Amiga Computer Community Portal Website 11 January 2010 15:55 UTC amigaworld.net [Source type: General]

.They use just-in-time translation to convert x86 instructions to the CPU's native instructions.^ Interrupt instructions The x86 CPU allows for interrupts .
• CSCI 350: Operating systems 11 January 2010 15:55 UTC ozark.hendrix.edu [Source type: Reference]

^ However, the CPU chips in Sun boxes are RISC chips (Reduced Instruction Set) so they are significantly faster than an Intel chip of a comparable clock speed.
• Installing Sun Solaris Intel 9 UNIX For x86 PC Installation 11 January 2010 15:55 UTC www.parkansky.com [Source type: General]

^ It uses instruction translation to convert the cumbersome x86 instruction set to high performance RISC-like instructions, and drives those RISC instructions with a state of the art microarchitecture.
• Paul Hsieh's 7th generation x86 CPU Comparisons 11 January 2010 15:55 UTC www.azillionmonkeys.com [Source type: FILTERED WITH BAYES]

.Transmeta argues that their approach allows for more power efficient designs since the CPU can forgo the complicated decode step of more traditional x86 implementations.^ I'm not a hardware guy (have worked on a CPU design but was involved more in the compiler side) but it seems that it makes more sense to be consistent.
• Slashdot Mobile Story | Intel and LG Team Up For x86 Smartphone 11 January 2010 15:55 UTC mobile.slashdot.org [Source type: General]

^ Since the x86-64 is fully IA32 compatible at power-on, it also needs to deal with getting the CPU out of 16-bit mode, in to 32-bit mode, and this time a couple of steps further, into 64-bit mode.
• Porting NetBSD to the AMD x86-641: a case study in OS portability 11 January 2010 15:55 UTC www.usenix.org [Source type: FILTERED WITH BAYES]
• Porting NetBSD to the AMD x86-641: a case study in OS portability 11 January 2010 15:55 UTC www.usenix.org [Source type: FILTERED WITH BAYES]

^ New multicore CPU's should only have one or two legacy cores, the rest should be more efficiently designed.
• AnandTech 11 January 2010 15:55 UTC www.anandtech.com [Source type: FILTERED WITH BAYES]

## Segmentation

.Minicomputers during the late 1970s were running up against the 16-bit 64-KB address limit, as memory had become cheaper.^ In the 8086, a memory address was computed as follows: Take the segment register, shift it left four bits, and add the address to this.
• CSCI 350: Operating systems 11 January 2010 15:55 UTC ozark.hendrix.edu [Source type: Reference]

^ A big change in Solaris 7 is its support for 64-bit virtual addresses on UltraSPARCs, in contrast to 2.6 which has only 64-bit file offsets.
• Solaris on Intel - x86 FAQ 11 January 2010 15:55 UTC www.menet.umn.edu [Source type: FILTERED WITH BAYES]

^ Upon finding the appropriate descriptor table entry, the processor checks permission bits (read, write, and execute) and compares the virtual address of the requested memory access against the segment limit in the descriptor table, throwing an exception if any of these checks fail.
• Vx32: Lightweight, User-level Sandboxing on the x86 11 January 2010 15:55 UTC pdos.csail.mit.edu [Source type: Reference]

.Most such companies therefore redesigned their processors to directly handle 32-bit addressing and data.^ Second, direct processor interconnections solve the problem of cache coherence by transferring the data directly from one CPU to another.
• A Glance at the Future: AMD Hammer Processors and x86-64 Technology - X-bit labs 11 January 2010 15:55 UTC www.xbitlabs.com [Source type: FILTERED WITH BAYES]

^ Vx32 performance is independent of the host operating system’s choice of processor mode, because vx32 always runs guest code in 32-bit mode.
• Vx32: Lightweight, User-level Sandboxing on the x86 11 January 2010 15:55 UTC pdos.csail.mit.edu [Source type: Reference]

^ The mapped-base functionality, which is used by 32-Bit applications that need a larger dynamic data space (such as database management systems), was replaced with flexmap.
• Release Notes for SUSE Linux Enterprise Server 11 11 January 2010 15:55 UTC www.novell.com [Source type: FILTERED WITH BAYES]

.The original 8086, developed from the simple 8085 microprocessor and primarily aiming at another market, instead adopted segment registers which raised the memory address limit by only 4 bits, to 20 bits (1 megabyte).^ So memory addresses used a second register --- the segment registers --- to work around this.
• CSCI 350: Operating systems 11 January 2010 15:55 UTC ozark.hendrix.edu [Source type: Reference]

^ The 8086 used 16-bit registers.
• CSCI 350: Operating systems 11 January 2010 15:55 UTC ozark.hendrix.edu [Source type: Reference]

^ Real mode was still limited to the one megabyte program addressing of the 8086, et al.
• PC Processors Guide by x86.org 11 January 2010 15:55 UTC www.rcollins.org [Source type: FILTERED WITH BAYES]

.While the concept of segment registers was not new at the time, as many mainframes used segment register to quickly swap to different tasks, in practice on the x86 it was (is) a much-criticized implementation.^ "Every x86 has a different implementation.
• Can the x86 Just Keep Going? - InternetNews.com 11 January 2010 15:55 UTC www.internetnews.com [Source type: General]

^ You could define one data segment for Task 1 and a different data segment for Task 2, but have the two segments overlap slightly.
• Embedded.com - Managing Tasks on x86 Processors 11 January 2010 15:55 UTC www.embedded.com [Source type: FILTERED WITH BAYES]

^ The thing is that Adobe does create new versions of their software in > > > less time than you state, just that they don't do it for Solaris on x86.
• OpenSolaris Forums : Adobe Acrobat for Solaris x86 ... 11 January 2010 15:55 UTC www.opensolaris.org [Source type: FILTERED WITH BAYES]

.Data and/or code could be managed within "near" 16-bit segments within this 1 MB address space, or a compiler could operate in a "far" mode using 32-bit segment:offset pairs reaching (only) 1 MB. While that would also prove to be quite limiting by the mid-1980s, it was working for the emerging PC market, and made it very simple to translate software from the older 8080, 8085, and Z80 to the newer processor.^ Size and address of the code segment are expected to be in 32-bit range, but data can be the full 64-bit range Large.
• Porting NetBSD to the AMD x86-641: a case study in OS portability 11 January 2010 15:55 UTC www.usenix.org [Source type: FILTERED WITH BAYES]
• Porting NetBSD to the AMD x86-641: a case study in OS portability 11 January 2010 15:55 UTC www.usenix.org [Source type: FILTERED WITH BAYES]

^ So memory addresses used a second register --- the segment registers --- to work around this.
• CSCI 350: Operating systems 11 January 2010 15:55 UTC ozark.hendrix.edu [Source type: Reference]

^ No restrictions on data or code addresses.
• Porting NetBSD to the AMD x86-641: a case study in OS portability 11 January 2010 15:55 UTC www.usenix.org [Source type: FILTERED WITH BAYES]
• Porting NetBSD to the AMD x86-641: a case study in OS portability 11 January 2010 15:55 UTC www.usenix.org [Source type: FILTERED WITH BAYES]

.In 1985, the 16 bit segment addressing model was effectively factored out by the introduction of 32-bit offset registers, in the 386 design.^ The 8086 used 16-bit registers.
• CSCI 350: Operating systems 11 January 2010 15:55 UTC ozark.hendrix.edu [Source type: Reference]

^ In the 8086, a memory address was computed as follows: Take the segment register, shift it left four bits, and add the address to this.
• CSCI 350: Operating systems 11 January 2010 15:55 UTC ozark.hendrix.edu [Source type: Reference]

^ A big change in Solaris 7 is its support for 64-bit virtual addresses on UltraSPARCs, in contrast to 2.6 which has only 64-bit file offsets.
• Solaris on Intel - x86 FAQ 11 January 2010 15:55 UTC www.menet.umn.edu [Source type: FILTERED WITH BAYES]

.In real mode, segmentation is achieved by shifting the segment address left by 4 bits and adding an offset in order to receive a final 20-bit address.^ Real mode was still limited to the one megabyte program addressing of the 8086, et al.
• PC Processors Guide by x86.org 11 January 2010 15:55 UTC www.rcollins.org [Source type: FILTERED WITH BAYES]

^ A big change in Solaris 7 is its support for 64-bit virtual addresses on UltraSPARCs, in contrast to 2.6 which has only 64-bit file offsets.
• Solaris on Intel - x86 FAQ 11 January 2010 15:55 UTC www.menet.umn.edu [Source type: FILTERED WITH BAYES]

^ The first argument is the target eip ; the second is the address of the end of the 32-bit jump offset to be patched.
• Vx32: Lightweight, User-level Sandboxing on the x86 11 January 2010 15:55 UTC pdos.csail.mit.edu [Source type: Reference]

For example, if DS is A000h and SI is 5677h, DS:SI will point at the absolute address DS × 16 + SI = A5677h. .Thus the total address space in real mode is 220 bytes, or 1 MB, quite an impressive figure for 1978. All memory addresses consist of both a segment and offset; every type of access (code, data, or stack) has a default segment register associated with it (for data the register is usually DS, for code it is CS, and for stack it is SS).^ So memory addresses used a second register --- the segment registers --- to work around this.
• CSCI 350: Operating systems 11 January 2010 15:55 UTC ozark.hendrix.edu [Source type: Reference]

^ No restrictions on data or code addresses.
• Porting NetBSD to the AMD x86-641: a case study in OS portability 11 January 2010 15:55 UTC www.usenix.org [Source type: FILTERED WITH BAYES]
• Porting NetBSD to the AMD x86-641: a case study in OS portability 11 January 2010 15:55 UTC www.usenix.org [Source type: FILTERED WITH BAYES]

^ And data is typically loaded relative to the ds (data segment) register.
• CSCI 350: Operating systems 11 January 2010 15:55 UTC ozark.hendrix.edu [Source type: Reference]

.For data accesses, the segment register can be explicitly specified (using a segment override prefix) to use any of the four segment registers.^ The vx32 runtime accesses the control segment by specifying a segment override on its data access instructions.
• Vx32: Lightweight, User-level Sandboxing on the x86 11 January 2010 15:55 UTC pdos.csail.mit.edu [Source type: Reference]

^ In the 8086, a memory address was computed as follows: Take the segment register, shift it left four bits, and add the address to this.
• CSCI 350: Operating systems 11 January 2010 15:55 UTC ozark.hendrix.edu [Source type: Reference]

^ The key to vx32’s combination of flexibility and efficiency is to use different mechanisms to sandbox data accesses and instruction execution.
• Vx32: Lightweight, User-level Sandboxing on the x86 11 January 2010 15:55 UTC pdos.csail.mit.edu [Source type: Reference]

.In this scheme, two different segment/offset pairs can point at a single absolute location.^ You could define one data segment for Task 1 and a different data segment for Task 2, but have the two segments overlap slightly.
• Embedded.com - Managing Tasks on x86 Processors 11 January 2010 15:55 UTC www.embedded.com [Source type: FILTERED WITH BAYES]

^ Here's where it gets weird: the TSS holds three different pairs of stack segments and pointers, one for each of the upper three privilege levels.
• Embedded.com - Managing Tasks on x86 Processors 11 January 2010 15:55 UTC www.embedded.com [Source type: FILTERED WITH BAYES]

^ The word stored into fs:[0x5c] is an fs -relative offset telling vxrun_lookup_backpatch where in the control segment to find the two dwords arguments at b7d8d115 .
• Vx32: Lightweight, User-level Sandboxing on the x86 11 January 2010 15:55 UTC pdos.csail.mit.edu [Source type: Reference]

Thus, if DS is A111h and SI is 4567h, DS:SI will point at the same A5677h as above. .This scheme makes it impossible to use more than four segments at once.^ Thank you for that, well that sounds good to me, and if Intel processors will be faster and more efficient than PowerPC, as Steve claims, then using them is logical.

^ Making drivers that work correctly with PAE on more than 32 bits is a bit more difficult.
• AnandTech 11 January 2010 15:55 UTC www.anandtech.com [Source type: FILTERED WITH BAYES]

^ This worked well enough, with the following restriction: Your old 8.x (SPARC) and 4.x (x86) plugin did not allow me to open more than 25 documents at once.
• OpenSolaris Forums : Adobe Acrobat for Solaris x86 ... 11 January 2010 15:55 UTC www.opensolaris.org [Source type: FILTERED WITH BAYES]

.CS and SS are vital for the correct functioning of the program, so that only DS and ES can be used to point to data segments outside the program (or, more precisely, outside the currently-executing segment of the program) or the stack.^ Using both Ethernet and iSCSI functions at the same time may hang the device and cause data loss and filesystem corruptions on iSCSI devices, or network disruptions on Ethernet.
• Release Notes for SUSE Linux Enterprise Server 11 11 January 2010 15:55 UTC www.novell.com [Source type: FILTERED WITH BAYES]

^ To restore STDERR, use Int 21h function 46h to force STDERR, again 2, to point to the filehandle saved from step 3 above.
• x86 Assembly Language FAQ - General Part 1/3 11 January 2010 15:55 UTC www.faqs.org [Source type: Reference]

^ Release all memory above the program using Int 21 function 4ah so that there will be room enough to load and execute the designated program.
• x86 Assembly Language FAQ - General Part 1/3 11 January 2010 15:55 UTC www.faqs.org [Source type: Reference]

.In protected mode, a segment register no longer contains the physical address of the beginning of a segment, but contain a "selector" that points to a system-level structure called a segment descriptor.^ These structures contain some information on the protection of the page, and point to the physical address of the page in which the structure to be indexed at the next (lower) level is contained.
• Porting NetBSD to the AMD x86-641: a case study in OS portability 11 January 2010 15:55 UTC www.usenix.org [Source type: FILTERED WITH BAYES]
• Porting NetBSD to the AMD x86-641: a case study in OS portability 11 January 2010 15:55 UTC www.usenix.org [Source type: FILTERED WITH BAYES]

^ When it runs in protected mode, a segment register is treated differently.
• CSCI 350: Operating systems 11 January 2010 15:55 UTC ozark.hendrix.edu [Source type: Reference]

^ The EIP register is initialized to 0000FFF0 H, and the CS register is a segment selector (value F000 H) which points to a base address of FFFF0000 H. Thus, execution begins at address FFFFFFF0 H, sixteen bytes from the top of physical memory, in an EPROM. The EPROM is usually located at a much lower physical address, but is being remapped to a high address by the system chipset (e.g.
• Guide to x86 Bootstrapping 11 January 2010 15:55 UTC www.nondot.org [Source type: FILTERED WITH BAYES]

.A segment descriptor contains the physical address of the beginning of the segment, the length of the segment, and access permissions to that segment.^ Memory segmentation through descriptors, describing the type, base address and length of a section of memory.
• Porting NetBSD to the AMD x86-641: a case study in OS portability 11 January 2010 15:55 UTC www.usenix.org [Source type: FILTERED WITH BAYES]
• Porting NetBSD to the AMD x86-641: a case study in OS portability 11 January 2010 15:55 UTC www.usenix.org [Source type: FILTERED WITH BAYES]

^ The lowest level of page tables contains the actual physical address to be referenced.
• Porting NetBSD to the AMD x86-641: a case study in OS portability 11 January 2010 15:55 UTC www.usenix.org [Source type: FILTERED WITH BAYES]
• Porting NetBSD to the AMD x86-641: a case study in OS portability 11 January 2010 15:55 UTC www.usenix.org [Source type: FILTERED WITH BAYES]

^ These structures contain some information on the protection of the page, and point to the physical address of the page in which the structure to be indexed at the next (lower) level is contained.
• Porting NetBSD to the AMD x86-641: a case study in OS portability 11 January 2010 15:55 UTC www.usenix.org [Source type: FILTERED WITH BAYES]
• Porting NetBSD to the AMD x86-641: a case study in OS portability 11 January 2010 15:55 UTC www.usenix.org [Source type: FILTERED WITH BAYES]

.The offset is checked against the length of the segment, with offsets referring to locations outside the segment causing an exception.^ In fact, vx32 rewrites any guest instructions referring to segment registers so that they raise a virtual illegal instruction exception.
• Vx32: Lightweight, User-level Sandboxing on the x86 11 January 2010 15:55 UTC pdos.csail.mit.edu [Source type: Reference]

^ To catch and isolate exceptions caused by guest code, vx32 needs to register its own signal handlers for processor exceptions such as segmentation faults and floating point exceptions.
• Vx32: Lightweight, User-level Sandboxing on the x86 11 January 2010 15:55 UTC pdos.csail.mit.edu [Source type: Reference]

^ One Windows vulnerability, MS04-011, was caused by inadequate checks on application-provided LDT segments: this was merely a bug in the OS and not an issue with custom segments in general.
• Vx32: Lightweight, User-level Sandboxing on the x86 11 January 2010 15:55 UTC pdos.csail.mit.edu [Source type: Reference]

.Offsets referring to locations inside the segment are combined with the physical address of the beginning of the segment to get the physical address corresponding to that offset.^ The EIP register is initialized to 0000FFF0 H, and the CS register is a segment selector (value F000 H) which points to a base address of FFFF0000 H. Thus, execution begins at address FFFFFFF0 H, sixteen bytes from the top of physical memory, in an EPROM. The EPROM is usually located at a much lower physical address, but is being remapped to a high address by the system chipset (e.g.
• Guide to x86 Bootstrapping 11 January 2010 15:55 UTC www.nondot.org [Source type: FILTERED WITH BAYES]

^ To recover this information, vx32 first locates the translation fragment containing the current eip and converts the eip ’s offset within the fragment to an offset from the guest code address corresponding to the fragment.
• Vx32: Lightweight, User-level Sandboxing on the x86 11 January 2010 15:55 UTC pdos.csail.mit.edu [Source type: Reference]

^ The translated code saves ebx back into the guest control segment, loads the target eip into ebx , and then jumps to vxrun_lookup_indirect , which locates and jumps to the cached fragment for the guest address in ebx .
• Vx32: Lightweight, User-level Sandboxing on the x86 11 January 2010 15:55 UTC pdos.csail.mit.edu [Source type: Reference]

.The segmented nature can make programming and compilers design difficult because the use of near and far pointers affect performance.^ I'm not a hardware guy (have worked on a CPU design but was involved more in the compiler side) but it seems that it makes more sense to be consistent.
• Slashdot Mobile Story | Intel and LG Team Up For x86 Smartphone 11 January 2010 15:55 UTC mobile.slashdot.org [Source type: General]

^ Release all memory above the program using Int 21 function 4ah so that there will be room enough to load and execute the designated program.
• x86 Assembly Language FAQ - General Part 1/3 11 January 2010 15:55 UTC www.faqs.org [Source type: Reference]

^ Host applications are, of course, free to use their own compilers and libraries and to design new system call interfaces.
• Vx32: Lightweight, User-level Sandboxing on the x86 11 January 2010 15:55 UTC pdos.csail.mit.edu [Source type: Reference]

Addressing modes for 16-bit x86 processors can be summarized by this formula:
$\begin{Bmatrix}CS:\\DS:\\SS:\\ES:\end{Bmatrix} \begin{bmatrix}\begin{Bmatrix}BX\\BP\end{Bmatrix}\end{bmatrix} + \begin{bmatrix}\begin{Bmatrix}SI\\DI\end{Bmatrix}\end{bmatrix} + \rm [displacement]$
Addressing modes for 32-bit address size on 32-bit or 64-bit x86 processors can be summarized by this formula:
$\begin{Bmatrix}CS:\\DS:\\SS:\\ES:\\FS:\\GS:\end{Bmatrix} \begin{bmatrix}\begin{Bmatrix}EAX\\EBX\\ECX\\EDX\\ESP\\EBP\\ESI\\EDI\end{Bmatrix}\end{bmatrix} + \begin{bmatrix}\begin{Bmatrix}EAX\\EBX\\ECX\\EDX\\EBP\\ESI\\EDI\end{Bmatrix}*\begin{Bmatrix}1\\2\\4\\8\end{Bmatrix}\end{bmatrix} + \rm [displacement]$
Addressing modes for 64-bit code on 64-bit x86 processors can be summarized by these formulas:
$\begin{Bmatrix}:\\FS:\\GS:\end{Bmatrix} \begin{bmatrix}{\rm general\;register}\end{bmatrix} + \begin{bmatrix}{\rm general\;register}*\begin{Bmatrix}1\\2\\4\\8\end{Bmatrix}\end{bmatrix} + \rm [displacement]$
and
RIP + [displacement]
.The 8086 had 64 KB of 8-bit (or alternatively 32 K-word of 16-bit) I/O space, and a 64 KB (one segment) stack in memory supported by hardware.^ The 8086 used 16-bit registers.
• CSCI 350: Operating systems 11 January 2010 15:55 UTC ozark.hendrix.edu [Source type: Reference]

^ In the 8086, a memory address was computed as follows: Take the segment register, shift it left four bits, and add the address to this.
• CSCI 350: Operating systems 11 January 2010 15:55 UTC ozark.hendrix.edu [Source type: Reference]

^ A big change in Solaris 7 is its support for 64-bit virtual addresses on UltraSPARCs, in contrast to 2.6 which has only 64-bit file offsets.
• Solaris on Intel - x86 FAQ 11 January 2010 15:55 UTC www.menet.umn.edu [Source type: FILTERED WITH BAYES]

Only words (2 bytes) can be pushed to the stack. .The stack grows downwards (toward numerically lower addresses), its bottom being pointed by SS:SP. There are 256 interrupts, which can be invoked by both hardware and software.^ A Mac isn't just the hardware and the software, it's both working seamlessly together.

^ I know some people say "It's the OS, stupid," but there really is a lot to be said for Apple's hardware design and the way it can weave the OS with the hardware to take advantage of both.

^ Both ways make sense, but the x86 designers had to choose one, and they clearly thought of address 0 being at the bottom.
• CSCI 350: Operating systems 11 January 2010 15:55 UTC ozark.hendrix.edu [Source type: Reference]

.The interrupts can cascade, using the stack to store the return address.^ The added push instruction saves the guest return address onto the stack.
• Vx32: Lightweight, User-level Sandboxing on the x86 11 January 2010 15:55 UTC pdos.csail.mit.edu [Source type: Reference]

^ Returning from the interrupt pops the ip and cs values from the stack, effectively transferring control back to what was executing before the interrupt occurred.
• CSCI 350: Operating systems 11 January 2010 15:55 UTC ozark.hendrix.edu [Source type: Reference]

• AnandTech 11 January 2010 15:55 UTC www.anandtech.com [Source type: FILTERED WITH BAYES]

## x86 registers

For a description of the general notion of a CPU register, see Processor register.

### 16-bit

.The original Intel 8086 and 8088 have fourteen 16-bit registers.^ The 8086 featured a 16-bit data bus, while the 8088 featured an 8-bit data bus.
• PC Processors Guide by x86.org 11 January 2010 15:55 UTC www.rcollins.org [Source type: FILTERED WITH BAYES]

^ The 8086 used 16-bit registers.
• CSCI 350: Operating systems 11 January 2010 15:55 UTC ozark.hendrix.edu [Source type: Reference]

^ And then the 16-bit Intel 8088 (1979) became the CPU for the first IBM PC. Subsequent generations became new CPUs for IBM PCs and their clones.
• CSCI 350: Operating systems 11 January 2010 15:55 UTC ozark.hendrix.edu [Source type: Reference]

.Four of them (AX, BX, CX, DX) are general registers (although each may have an additional purpose; for example only CX can be used as a counter with the loop instruction).^ Guest code may freely use all eight general-purpose registers provided by the x86 architecture: vx32 avoids both the dynamic register renaming and spilling of translation engines like Valgrind [34] and the static register usage restrictions of SFI [42].
• Vx32: Lightweight, User-level Sandboxing on the x86 11 January 2010 15:55 UTC pdos.csail.mit.edu [Source type: Reference]

^ For example, you might have NetBSD on your first and only SCSI disk (you do use SCSI , don't you?
• Guide to x86 Bootstrapping 11 January 2010 15:55 UTC www.nondot.org [Source type: FILTERED WITH BAYES]

^ The eip register is the instruction pointer (often called the program counter).
• CSCI 350: Operating systems 11 January 2010 15:55 UTC ozark.hendrix.edu [Source type: Reference]

Each can be accessed as two separate bytes (thus BX's high byte can be accessed as BH and low byte as BL). .Four segment registers (CS, DS, SS and ES) are used to form a memory address.^ So memory addresses used a second register --- the segment registers --- to work around this.
• CSCI 350: Operating systems 11 January 2010 15:55 UTC ozark.hendrix.edu [Source type: Reference]

^ The last block of six registers, cs through gs , are the segment registers , used for memory addressing.
• CSCI 350: Operating systems 11 January 2010 15:55 UTC ozark.hendrix.edu [Source type: Reference]

^ The EIP register is initialized to 0000FFF0 H, and the CS register is a segment selector (value F000 H) which points to a base address of FFFF0000 H. Thus, execution begins at address FFFFFFF0 H, sixteen bytes from the top of physical memory, in an EPROM. The EPROM is usually located at a much lower physical address, but is being remapped to a high address by the system chipset (e.g.
• Guide to x86 Bootstrapping 11 January 2010 15:55 UTC www.nondot.org [Source type: FILTERED WITH BAYES]

.There are two pointer registers.^ It is common nowadays for thread libraries to use one of these two segment registers— fs or gs —as a pointer to thread-local storage.
• Vx32: Lightweight, User-level Sandboxing on the x86 11 January 2010 15:55 UTC pdos.csail.mit.edu [Source type: Reference]

.SP points to the bottom of the stack and BP which is used to point at some other place in the stack, typically above the local variables.^ The floating point is somewhat degraded in some features and somewhat improved in others relative to the P6 architecture.
• Paul Hsieh's 7th generation x86 CPU Comparisons 11 January 2010 15:55 UTC www.azillionmonkeys.com [Source type: FILTERED WITH BAYES]

^ Look at their C6000 series and C6400+ , also in the dsp unit in their OMAP cores used in a lot of mobile phones and in the dsps used in some base stations and a lot of other comms equipment.
• AnandTech 11 January 2010 15:55 UTC www.anandtech.com [Source type: FILTERED WITH BAYES]

^ Softlinks that are relative to route (e.g., /usr/local pointing to /local) will point to the wrong place.
• Solaris on Intel - x86 FAQ 11 January 2010 15:55 UTC www.menet.umn.edu [Source type: FILTERED WITH BAYES]

Two registers (SI and DI) are for array indexing. .The FLAGS register contains flags such as carry flag, overflow flag and zero flag.^ It would also set the flags: in this case, the top bit is 1, so the sign flag would be set to 1; the result isn't zero, so the result flag would be reset to 0; and the carry and overflow flags would be reset to 0, since there is no carry and no overflow (not even the possibility).
• CSCI 350: Operating systems 11 January 2010 15:55 UTC ozark.hendrix.edu [Source type: Reference]

^ Zeroes are shifted into the empty places, and the last bit shifted out goes into the carry flag.
• CSCI 350: Operating systems 11 January 2010 15:55 UTC ozark.hendrix.edu [Source type: Reference]

^ The overflow flag is set if the computation, interpreted as a signed computation, goes beyond the capacity of the register.
• CSCI 350: Operating systems 11 January 2010 15:55 UTC ozark.hendrix.edu [Source type: Reference]

.Finally, the instruction pointer (IP) points to the next instruction that will be fetched from memory and then executed.^ It includes the support of segmented memory and the 32bit GPRs and instruction pointer.
• A Glance at the Future: AMD Hammer Processors and x86-64 Technology - X-bit labs 11 January 2010 15:55 UTC www.xbitlabs.com [Source type: FILTERED WITH BAYES]

^ In effect, this restores the previous value of eip , so that the next instruction executed is the instruction following the call that put us there.
• CSCI 350: Operating systems 11 January 2010 15:55 UTC ozark.hendrix.edu [Source type: Reference]

^ The 21264 pipeline is structured with a maximum of 2 memory, integer, or FP instructions, from which any combination of executing 4 can be sustained per clock.
• Paul Hsieh's 7th generation x86 CPU Comparisons 11 January 2010 15:55 UTC www.azillionmonkeys.com [Source type: FILTERED WITH BAYES]

### 32-bit

.With the advent of the 32-bit 80386 processor, the 16-bit general-purpose registers, base registers, index registers, instruction pointer, and FLAGS register, but not the segment registers, were expanded to 32 bits.^ The 8086 used 16-bit registers.
• CSCI 350: Operating systems 11 January 2010 15:55 UTC ozark.hendrix.edu [Source type: Reference]

^ So, 64bit mode features the support of: 64bit virtual addresses; 8 new 64bit general-purpose registers; GPRs extension to 64bit (including the "old" EAX, EBX and so on); 64-bitinstruction pointer; New relative instruction pointer (RIP) method of data-addressing; Continuous address space with a single space for instructions, data and the stack.
• A Glance at the Future: AMD Hammer Processors and x86-64 Technology - X-bit labs 11 January 2010 15:55 UTC www.xbitlabs.com [Source type: FILTERED WITH BAYES]

^ And then the 16-bit Intel 8088 (1979) became the CPU for the first IBM PC. Subsequent generations became new CPUs for IBM PCs and their clones.
• CSCI 350: Operating systems 11 January 2010 15:55 UTC ozark.hendrix.edu [Source type: Reference]

.This is represented by prefixing an "E" (for Extended) to the register names in x86 assembly language.^ There's a variety of x86 assembly languages.
• CSCI 350: Operating systems 11 January 2010 15:55 UTC ozark.hendrix.edu [Source type: Reference]

^ In this case, the subroutine is contrived --- it's too simple to be useful ---, but it illustrates how you can write a subroutine in x86 assembly language.
• CSCI 350: Operating systems 11 January 2010 15:55 UTC ozark.hendrix.edu [Source type: Reference]

^ The vx32 sandbox library consists of 3,800 lines of C (1,500 semicolons) and 500 lines of x86 assembly language.
• Vx32: Lightweight, User-level Sandboxing on the x86 11 January 2010 15:55 UTC pdos.csail.mit.edu [Source type: Reference]

.Thus, the AX register corresponds to the lowest 16 bits of the new 32-bit EAX register, SI corresponds to the lowest 16 bits of ESI, and so on.^ The 8086 used 16-bit registers.
• CSCI 350: Operating systems 11 January 2010 15:55 UTC ozark.hendrix.edu [Source type: Reference]

^ And then the 16-bit Intel 8088 (1979) became the CPU for the first IBM PC. Subsequent generations became new CPUs for IBM PCs and their clones.
• CSCI 350: Operating systems 11 January 2010 15:55 UTC ozark.hendrix.edu [Source type: Reference]

^ Compatibility mode provides binary compatibility of the existing 16- and 32-bit applications with the 64bit operation system.
• A Glance at the Future: AMD Hammer Processors and x86-64 Technology - X-bit labs 11 January 2010 15:55 UTC www.xbitlabs.com [Source type: FILTERED WITH BAYES]

.The general-purpose registers, base registers, and index registers can all be used as the base in addressing modes, and all of those registers except for the stack pointer can be used as the index in addressing modes.^ So, 64bit mode features the support of: 64bit virtual addresses; 8 new 64bit general-purpose registers; GPRs extension to 64bit (including the "old" EAX, EBX and so on); 64-bitinstruction pointer; New relative instruction pointer (RIP) method of data-addressing; Continuous address space with a single space for instructions, data and the stack.
• A Glance at the Future: AMD Hammer Processors and x86-64 Technology - X-bit labs 11 January 2010 15:55 UTC www.xbitlabs.com [Source type: FILTERED WITH BAYES]

^ (The esi and edi registers are designed for this purpose: The names stand for source index and destination index , respectively.
• CSCI 350: Operating systems 11 January 2010 15:55 UTC ozark.hendrix.edu [Source type: Reference]

^ Certain graphics, symbols, and terms used on this site and in its documents are registered trademarks of their respective owners and are contained herein for identification purposes only.
• Installing Sun Solaris Intel 9 UNIX For x86 PC Installation 11 January 2010 15:55 UTC www.parkansky.com [Source type: General]

.Two new segment registers (FS and GS) were added.^ Vx32 executes guest code with the processor’s fs or gs register holding the selector for the guest control segment.
• Vx32: Lightweight, User-level Sandboxing on the x86 11 January 2010 15:55 UTC pdos.csail.mit.edu [Source type: Reference]

^ It is common nowadays for thread libraries to use one of these two segment registers— fs or gs —as a pointer to thread-local storage.
• Vx32: Lightweight, User-level Sandboxing on the x86 11 January 2010 15:55 UTC pdos.csail.mit.edu [Source type: Reference]

^ Very simply: a few new registers were added to the register set, and the existing ones were extended: .
• A Glance at the Future: AMD Hammer Processors and x86-64 Technology - X-bit labs 11 January 2010 15:55 UTC www.xbitlabs.com [Source type: FILTERED WITH BAYES]

.With a greater number of registers, instructions and operands, the machine code format was expanded.^ The partition you selected does not have the proper magic number (a special code used to identify formatted partitions).
• Guide to x86 Bootstrapping 11 January 2010 15:55 UTC www.nondot.org [Source type: FILTERED WITH BAYES]

^ An instruction set which replicates the same operation over multiple operands which are themselves packed into wide registers.
• Paul Hsieh's 7th generation x86 CPU Comparisons 11 January 2010 15:55 UTC www.azillionmonkeys.com [Source type: FILTERED WITH BAYES]

^ A mov instruction can move a number, a register value, or a value in memory into either a register or a memory location, except that a single mov cannot copy directly from one memory location to another.
• CSCI 350: Operating systems 11 January 2010 15:55 UTC ozark.hendrix.edu [Source type: Reference]

.To provide backward compatibility, segments with executable code can be marked as containing either 16-bit or 32-bit instructions.^ Compatibility mode provides binary compatibility of the existing 16- and 32-bit applications with the 64bit operation system.
• A Glance at the Future: AMD Hammer Processors and x86-64 Technology - X-bit labs 11 January 2010 15:55 UTC www.xbitlabs.com [Source type: FILTERED WITH BAYES]

^ However, the operation system regards the mechanisms used for address translation, work with interrupts and exceptions, and system data structures as if they were of 64bit Long Mode; As an addition to Long mode, x86-64 is supposed to support Legacy mode thus providing binary compatibility with 16- and 32-bit operation systems.
• A Glance at the Future: AMD Hammer Processors and x86-64 Technology - X-bit labs 11 January 2010 15:55 UTC www.xbitlabs.com [Source type: FILTERED WITH BAYES]

^ The engine runs an emulation program (the Code Morpher ) which reads x86 instructions and compiles them to VLIW code snippets, then executes the compiled snippets.
• Paul Hsieh's 7th generation x86 CPU Comparisons 11 January 2010 15:55 UTC www.azillionmonkeys.com [Source type: FILTERED WITH BAYES]

.Special prefixes allow inclusion of 32-bit instructions in a 16-bit segment or vice versa.^ Compatibility mode provides binary compatibility of the existing 16- and 32-bit applications with the 64bit operation system.
• A Glance at the Future: AMD Hammer Processors and x86-64 Technology - X-bit labs 11 January 2010 15:55 UTC www.xbitlabs.com [Source type: FILTERED WITH BAYES]

^ The picoJava VM would be able to read and write x86 state through special APIs, however, in ordinary operation be otherwise totally isolated from the x86 state and vice versa.
• Paul Hsieh's 7th generation x86 CPU Comparisons 11 January 2010 15:55 UTC www.azillionmonkeys.com [Source type: FILTERED WITH BAYES]

^ The eax register holds 32 bits, but you can refer to its lower 16 bits using ax , and within ax you can refer to its higher 8 bits with ah and the lower 8 bits with al .
• CSCI 350: Operating systems 11 January 2010 15:55 UTC ozark.hendrix.edu [Source type: Reference]

### 64-bit

.Starting with the AMD Opteron processor, the x86 in 64-bit long mode (as a subset of x86-64 mode) extended the 32-bit registers in a way similar to how the 16 to 32-bit protected mode extension was done (RAX, RBX, RCX, RDX, RSI, RDI, RBP, RSP, RFLAGS, RIP).^ AMD used a similar approach to the development of the 64-bit architecture.
• A Glance at the Future: AMD Hammer Processors and x86-64 Technology - X-bit labs 11 January 2010 15:55 UTC www.xbitlabs.com [Source type: FILTERED WITH BAYES]

^ It refers to the fact that the x86 word is 16 bits long, so 32-bit data is two words long.
• CSCI 350: Operating systems 11 January 2010 15:55 UTC ozark.hendrix.edu [Source type: Reference]

^ The 8086 used 16-bit registers.
• CSCI 350: Operating systems 11 January 2010 15:55 UTC ozark.hendrix.edu [Source type: Reference]

.However, 8 additional 64-bit general registers (R8, R9, ..., R15) were also introduced.^ As you see, there are 8 more R8-R15 general-purpose registers (GPR), which are used in the 64bit mode (it means that they require programs recompilation) and the existing EAX, EBX and so on are extended from 32bit to 64bit.
• A Glance at the Future: AMD Hammer Processors and x86-64 Technology - X-bit labs 11 January 2010 15:55 UTC www.xbitlabs.com [Source type: FILTERED WITH BAYES]

^ Additionally, a mov can copy between a segment registers and a general register --- this gives you a way of accessing these segment registers when needed.
• CSCI 350: Operating systems 11 January 2010 15:55 UTC ozark.hendrix.edu [Source type: Reference]

^ As for the addition of proprietary x86 instructions, wasn't AMD the company that added 64 bit instructions to the x86 instruction set?
• AnandTech 11 January 2010 15:55 UTC www.anandtech.com [Source type: FILTERED WITH BAYES]

.The addressing modes were not dramatically changed from 32-bit mode, except that addressing was extended to 64 bits, physical addressing was now sign extended (so memory always added equally to the top and bottom of memory; note that this does not affect linear or virtual addressing), and other selector details were dramatically reduced.^ In PAE, the page tables map 32 bit virtual addresses to 36 bit physical addresses.
• AnandTech 11 January 2010 15:55 UTC www.anandtech.com [Source type: FILTERED WITH BAYES]

^ That is, the 64bit mode is the 64-bitness as it is.
• A Glance at the Future: AMD Hammer Processors and x86-64 Technology - X-bit labs 11 January 2010 15:55 UTC www.xbitlabs.com [Source type: FILTERED WITH BAYES]

^ So far the G5 mac massive advantage is in being able to have 16GB RAM, and to top it off, the PowerPC 970 processor is capable of addressing 4 terrabytes of physical memory, but it does not mention anywhere, that they ever did this.
• Amigaworld.net - The Amiga Computer Community Portal Website 11 January 2010 15:55 UTC amigaworld.net [Source type: General]

### Miscellaneous/Special Purpose

x86 processors also include various special/miscellaneous registers such as control registers (CR0 through 4), debug registers (DR0 through 3, plus 6 and 7), test registers (TR4 through 7), descriptor registers (GDTR, LDTR, IDTR), and a task register (TR).

### Purpose

Although the main registers (with the exception of the instruction pointer) are "general-purpose" and can be used for anything, it was envisioned that they be used for the following purposes:
.
• AX/EAX/RAX: accumulator
• BX/EBX/RBX: base index (ex: arrays)
• CX/ECX/RCX: counter
• DX/EDX/RDX: data/general
• SI/ESI/RSI: "source index" for string operations.
• DI/EDI/RDI: "destination index" for string operations.
• SP/ESP/RSP: stack pointer for top address of the stack.
• BP/EBP/RBP: stack base pointer for holding the address of the current stack frame.
• IP/EIP/RIP: instruction pointer.^ The eip register is the instruction pointer (often called the program counter).
• CSCI 350: Operating systems 11 January 2010 15:55 UTC ozark.hendrix.edu [Source type: Reference]

^ The pushad and popad instructions are for saving several the general registers at once: pushad pushes eax , ecx , edx , ebx , esp , ebp , esi (in that order), and edi , and popad pops them in reverse order.
• CSCI 350: Operating systems 11 January 2010 15:55 UTC ozark.hendrix.edu [Source type: Reference]

^ So, 64bit mode features the support of: 64bit virtual addresses; 8 new 64bit general-purpose registers; GPRs extension to 64bit (including the "old" EAX, EBX and so on); 64-bitinstruction pointer; New relative instruction pointer (RIP) method of data-addressing; Continuous address space with a single space for instructions, data and the stack.
• A Glance at the Future: AMD Hammer Processors and x86-64 Technology - X-bit labs 11 January 2010 15:55 UTC www.xbitlabs.com [Source type: FILTERED WITH BAYES]

Holds the program counter, the current instruction address.
.No particular purposes were envisioned for the other 8 registers available only in 64-bit mode.^ That is, the 64bit mode is the 64-bitness as it is.
• A Glance at the Future: AMD Hammer Processors and x86-64 Technology - X-bit labs 11 January 2010 15:55 UTC www.xbitlabs.com [Source type: FILTERED WITH BAYES]

^ A big change in Solaris 7 is its support for 64-bit virtual addresses on UltraSPARCs, in contrast to 2.6 which has only 64-bit file offsets.
• Solaris on Intel - x86 FAQ 11 January 2010 15:55 UTC www.menet.umn.edu [Source type: FILTERED WITH BAYES]

^ The shock was due to the fact that the only 64-bit processor then was Intel Itanium.
• A Glance at the Future: AMD Hammer Processors and x86-64 Technology - X-bit labs 11 January 2010 15:55 UTC www.xbitlabs.com [Source type: FILTERED WITH BAYES]

.Some instructions compiled and executed more efficiently when using these registers for their designed purpose.^ I'm not a hardware guy (have worked on a CPU design but was involved more in the compiler side) but it seems that it makes more sense to be consistent.
• Slashdot Mobile Story | Intel and LG Team Up For x86 Smartphone 11 January 2010 15:55 UTC mobile.slashdot.org [Source type: General]

^ (The esi and edi registers are designed for this purpose: The names stand for source index and destination index , respectively.
• CSCI 350: Operating systems 11 January 2010 15:55 UTC ozark.hendrix.edu [Source type: Reference]

^ The reason for these two instructions is that occasionally there is a sequence of instructions that must be executed without interruption.
• CSCI 350: Operating systems 11 January 2010 15:55 UTC ozark.hendrix.edu [Source type: Reference]

.For example, using AL as an accumulator and adding an immediate byte value to it produces the efficient add to AL opcode of 04h, whilst using the BL register produces the generic and longer add to register opcode of 80C3h.^ How can they do that when producing an ARM processor cost only ARMs royalty + costs added on from many producers (Texas instruments qualcomm et al).
• Slashdot Mobile Story | Intel and LG Team Up For x86 Smartphone 11 January 2010 15:55 UTC mobile.slashdot.org [Source type: General]

^ The eax register holds 32 bits, but you can refer to its lower 16 bits using ax , and within ax you can refer to its higher 8 bits with ah and the lower 8 bits with al .
• CSCI 350: Operating systems 11 January 2010 15:55 UTC ozark.hendrix.edu [Source type: Reference]

^ For example, rol al, 1 will shift every bit in al left one spot, with the highest-order bit being rotated around into the lowest bit of the register.
• CSCI 350: Operating systems 11 January 2010 15:55 UTC ozark.hendrix.edu [Source type: Reference]

.An other example is double precision division and multiplication that works specifically with the AX and DX registers.^ Can we multiply using a different result register than AX:DX (this one has always annoyed me) .
• Slashdot Mobile Story | Intel and LG Team Up For x86 Smartphone 11 January 2010 15:55 UTC mobile.slashdot.org [Source type: General]

.Modern compilers benefited from the introduction of the sib byte ("scaled index byte") that allows to treat the registers uniformly (minicomputer-like).^ While this works for ARM too, x86 hardware can treat the near part of the stack almost like registers.
• Slashdot Mobile Story | Intel and LG Team Up For x86 Smartphone 11 January 2010 15:55 UTC mobile.slashdot.org [Source type: General]

.Some special instructions lost priority in the hardware design and became slower than equivalent small code sequences.^ Dynamic instruction translation is frequently used for purposes other than sandboxing, such as dynamic optimization [4], emulating other hardware platforms [9,44] or code instrumentation and debugging [28,34].
• Vx32: Lightweight, User-level Sandboxing on the x86 11 January 2010 15:55 UTC pdos.csail.mit.edu [Source type: Reference]

^ The vx32 virtual machine separates data sandboxing from code sandboxing, using different, complementary mechanisms for each: x86 segmentation hardware to sandbox data references and dynamic instruction translation to sandbox code.
• Vx32: Lightweight, User-level Sandboxing on the x86 11 January 2010 15:55 UTC pdos.csail.mit.edu [Source type: Reference]

A notable example is the LODSW instruction.

### Structure

General Purpose Registers (A, B, C and D)
64 56 48 40 32 24 16 8
R?X
E?X
?X
?H ?L
Segment Registers (C, D, S, E, F, and G)
64 56 48 40 32 24 16 8
?S
Pointer Registers (S and B)
64 56 48 40 32 24 16 8
R?P
E?P
?P
Index Registers (S and D)
64 56 48 40 32 24 16 8
R?I
E?I
?I
Instruction Pointer Register (I)
64 56 48 40 32 24 16 8
R?P
E?P
?P
x86-64-only General Purpose Registers (R8, R9, R10, R11, R12, R13, R14, R15)
64 56 48 40 32 24 16 8
?
?D

## Operating modes

### Real mode

.Real mode is an operating mode of 8086 and later x86-compatible CPUs.^ The core chip is not an x86 compatible CPU at all, but rather a VLIW engine.
• Paul Hsieh's 7th generation x86 CPU Comparisons 11 January 2010 15:55 UTC www.azillionmonkeys.com [Source type: FILTERED WITH BAYES]

^ The K7 This is the latest x86 compatible architecture from AMD. It is instruction set compatible with Intel's Pentium II CPUs.
• Paul Hsieh's 7th generation x86 CPU Comparisons 11 January 2010 15:55 UTC www.azillionmonkeys.com [Source type: FILTERED WITH BAYES]

^ While the 8086 was slow to take off, its underlying architecture -- later referred to as x86 -- would become one of technology's most impressive success stories.
• Happy birthday, x86! An industry standard turns 30 11 January 2010 15:55 UTC www.computerworld.com [Source type: News]

.Real mode is characterized by a 20 bit segmented memory address space (meaning that only 1 MB of memory can be addressed), direct software access to BIOS routines and peripheral hardware, and no concept of memory protection or multitasking at the hardware level.^ A big change in Solaris 7 is its support for 64-bit virtual addresses on UltraSPARCs, in contrast to 2.6 which has only 64-bit file offsets.
• Solaris on Intel - x86 FAQ 11 January 2010 15:55 UTC www.menet.umn.edu [Source type: FILTERED WITH BAYES]

^ However, a Sparc 4 or 5 will run Solaris 9 just fine so for a single-user system there's really no need to lay out the extra cash for a 20.
• Installing Sun Solaris Intel 9 UNIX For x86 PC Installation 11 January 2010 15:55 UTC www.parkansky.com [Source type: General]

^ Hot-Add-memory is currently only supported on the following hardware: .
• Release Notes for SUSE Linux Enterprise Server 11 11 January 2010 15:55 UTC www.novell.com [Source type: FILTERED WITH BAYES]

.All x86 CPUs in the 80286 series and later start up in real mode at power-on; 80186 CPUs and earlier had only one operational mode, which is equivalent to real mode in later chips.^ One x86 to rule them all?
• Slashdot Mobile Story | Intel and LG Team Up For x86 Smartphone 11 January 2010 15:55 UTC mobile.slashdot.org [Source type: General]

^ Re:One x86 to rule them all?
• Slashdot Mobile Story | Intel and LG Team Up For x86 Smartphone 11 January 2010 15:55 UTC mobile.slashdot.org [Source type: General]

^ X86 processors -- from the 8086 through the 80186, 80286, 80386, 80486 and various Pentium models, right down to today's multicore chips and processors for mobile applications -- have over time incorporated a growing x86 instruction set, but each has offered backward compatibility with earlier members of the family.
• Happy birthday, x86! An industry standard turns 30 11 January 2010 15:55 UTC www.computerworld.com [Source type: News]

.In order to use more than 64 KB of memory, the segment registers must be used.^ Thank you for that, well that sounds good to me, and if Intel processors will be faster and more efficient than PowerPC, as Steve claims, then using them is logical.

^ Also, some 64-bit x86 operating systems (e.g., Linux) use privileged instructions to initialize the thread-local segment register with a base that is impossible to represent in an ordinary 32-bit segment descriptor.
• Vx32: Lightweight, User-level Sandboxing on the x86 11 January 2010 15:55 UTC pdos.csail.mit.edu [Source type: Reference]

^ During any memory access, the processor uses the value in one of these segment registers as an index into one of two segment translation tables, the global descriptor table (GDT) or local descriptor table (LDT).
• Vx32: Lightweight, User-level Sandboxing on the x86 11 January 2010 15:55 UTC pdos.csail.mit.edu [Source type: Reference]

.This created great complications for C compiler implementors who introduced odd pointer modes such as "near", "far" and "huge" to lever the implicit nature of segmented architecture to different degrees, with some pointers containing 16-bit offsets within implied segments and other pointers containing segment addresses and offsets within segments.^ Also, values for MaxPClk for some cards are way too low in 16-bit and 24-bit modes in the /usr/openwin/share/etc/devdata/SUNWaccel/boards file.
• Solaris on Intel - x86 FAQ 11 January 2010 15:55 UTC www.menet.umn.edu [Source type: FILTERED WITH BAYES]

^ A big change in Solaris 7 is its support for 64-bit virtual addresses on UltraSPARCs, in contrast to 2.6 which has only 64-bit file offsets.
• Solaris on Intel - x86 FAQ 11 January 2010 15:55 UTC www.menet.umn.edu [Source type: FILTERED WITH BAYES]

^ To configure Xsun to use 16-bit color, configure using kdmconfig for the desired resolution in 256 color mode.
• Solaris on Intel - x86 FAQ 11 January 2010 15:55 UTC www.menet.umn.edu [Source type: FILTERED WITH BAYES]

### Protected mode

.In addition to real mode, the Intel 80286 supports protected mode, expanding addressable physical memory to 16 MB and addressable virtual memory to 1 GB, and providing protected memory, which prevents programs from corrupting one another.^ Solaris/x86 7 should support Intel's Extended Server Memory Architecture, with its 36-bit physical memory addresses (64 GBmemory), on Pentium Pro, Pentium II Xeon, and beyond.
• Solaris on Intel - x86 FAQ 11 January 2010 15:55 UTC www.menet.umn.edu [Source type: FILTERED WITH BAYES]

^ On a system with 1 GB of physical memory, the Automated Installer might not create swap space which causes the installation to hang due to insufficient memory.
• ReleaseNotes2008.11 (Project indiana.x86) - XWiki 11 January 2010 15:55 UTC hub.opensolaris.org [Source type: Reference]

^ They're cheap but if you have more that 16 MB of memory in your system you shouldn't be running an ISA disk controller.
• Solaris on Intel - x86 FAQ 11 January 2010 15:55 UTC www.menet.umn.edu [Source type: FILTERED WITH BAYES]

.This is done by using the segment registers only for storing an index to a segment table.^ Certain graphics, symbols, and terms used on this site and in its documents are registered trademarks of their respective owners and are contained herein for identification purposes only.
• Installing Sun Solaris Intel 9 UNIX For x86 PC Installation 11 January 2010 15:55 UTC www.parkansky.com [Source type: General]

^ During any memory access, the processor uses the value in one of these segment registers as an index into one of two segment translation tables, the global descriptor table (GDT) or local descriptor table (LDT).
• Vx32: Lightweight, User-level Sandboxing on the x86 11 January 2010 15:55 UTC pdos.csail.mit.edu [Source type: Reference]

^ It is common nowadays for thread libraries to use one of these two segment registers— fs or gs —as a pointer to thread-local storage.
• Vx32: Lightweight, User-level Sandboxing on the x86 11 January 2010 15:55 UTC pdos.csail.mit.edu [Source type: Reference]

.There were two such tables, the Global Descriptor Table (GDT) and the Local Descriptor Table (LDT), each holding up to 8192 segment descriptors, each segment giving access to 64 KB of memory.^ During any memory access, the processor uses the value in one of these segment registers as an index into one of two segment translation tables, the global descriptor table (GDT) or local descriptor table (LDT).
• Vx32: Lightweight, User-level Sandboxing on the x86 11 January 2010 15:55 UTC pdos.csail.mit.edu [Source type: Reference]

^ Upon finding the appropriate descriptor table entry, the processor checks permission bits (read, write, and execute) and compares the virtual address of the requested memory access against the segment limit in the descriptor table, throwing an exception if any of these checks fail.
• Vx32: Lightweight, User-level Sandboxing on the x86 11 January 2010 15:55 UTC pdos.csail.mit.edu [Source type: Reference]

^ Vx32 executes guest code with the processor’s ds , es , and ss registers holding the selector for the guest data segment, so that data reads and writes performed by the guest access this segment by default.
• Vx32: Lightweight, User-level Sandboxing on the x86 11 January 2010 15:55 UTC pdos.csail.mit.edu [Source type: Reference]

.The segment table provided a 24-bit base address, which can be added to the desired offset to create an absolute address.^ A big change in Solaris 7 is its support for 64-bit virtual addresses on UltraSPARCs, in contrast to 2.6 which has only 64-bit file offsets.
• Solaris on Intel - x86 FAQ 11 January 2010 15:55 UTC www.menet.umn.edu [Source type: FILTERED WITH BAYES]

^ The first argument is the target eip ; the second is the address of the end of the 32-bit jump offset to be patched.
• Vx32: Lightweight, User-level Sandboxing on the x86 11 January 2010 15:55 UTC pdos.csail.mit.edu [Source type: Reference]

^ Vx32 requires that the host OS provide a method of inserting custom segment descriptors into the application’s local descriptor table (LDT), as explained below.
• Vx32: Lightweight, User-level Sandboxing on the x86 11 January 2010 15:55 UTC pdos.csail.mit.edu [Source type: Reference]

.Each segment can be assigned one of four ring levels used for hardware-based computer security.^ Figure 9 shows the performance of vx32-based decoders compared to native ones on the four test architectures.
• Vx32: Lightweight, User-level Sandboxing on the x86 11 January 2010 15:55 UTC pdos.csail.mit.edu [Source type: Reference]

^ It is common nowadays for thread libraries to use one of these two segment registers— fs or gs —as a pointer to thread-local storage.
• Vx32: Lightweight, User-level Sandboxing on the x86 11 January 2010 15:55 UTC pdos.csail.mit.edu [Source type: Reference]

^ Today’s x86 operating systems typically make segmentation translation a no-op by using a base of 0 and a limit of 2 32 -1.
• Vx32: Lightweight, User-level Sandboxing on the x86 11 January 2010 15:55 UTC pdos.csail.mit.edu [Source type: Reference]

.The Intel 80386 introduced support in protected mode for paging, a mechanism making it possible to use virtual memory.^ Huge Page Memory support on POWER .
• Release Notes for SUSE Linux Enterprise Server 11 11 January 2010 15:55 UTC www.novell.com [Source type: FILTERED WITH BAYES]

^ Using vx32 means that 9vx requires no special kernel support to make it possible to run Plan 9 programs and native Unix programs side-by-side, sharing the same resources.
• Vx32: Lightweight, User-level Sandboxing on the x86 11 January 2010 15:55 UTC pdos.csail.mit.edu [Source type: Reference]

^ The highest performance increase is expected from apps that make copious use of the memory and switch very often between the threads.
• A Glance at the Future: AMD Hammer Processors and x86-64 Technology - X-bit labs 11 January 2010 15:55 UTC www.xbitlabs.com [Source type: FILTERED WITH BAYES]

.Paging is used extensively by modern multitasking operating systems.^ Although these features are not strictly required by vx32, they are, once again, provided by all widely-used x86 operating systems.
• Vx32: Lightweight, User-level Sandboxing on the x86 11 January 2010 15:55 UTC pdos.csail.mit.edu [Source type: Reference]

^ Today’s x86 operating systems typically make segmentation translation a no-op by using a base of 0 and a limit of 2 32 -1.
• Vx32: Lightweight, User-level Sandboxing on the x86 11 January 2010 15:55 UTC pdos.csail.mit.edu [Source type: Reference]

^ Again, all widely-used x86 operating systems have this capability.
• Vx32: Lightweight, User-level Sandboxing on the x86 11 January 2010 15:55 UTC pdos.csail.mit.edu [Source type: Reference]

.Linux, 386BSD and Windows NT were developed for the 386 because it was the first Intel architecture CPU to support paging and 32-bit segment offsets.^ A big change in Solaris 7 is its support for 64-bit virtual addresses on UltraSPARCs, in contrast to 2.6 which has only 64-bit file offsets.
• Solaris on Intel - x86 FAQ 11 January 2010 15:55 UTC www.menet.umn.edu [Source type: FILTERED WITH BAYES]

^ Vx32 performance is independent of the host operating system’s choice of processor mode, because vx32 always runs guest code in 32-bit mode.
• Vx32: Lightweight, User-level Sandboxing on the x86 11 January 2010 15:55 UTC pdos.csail.mit.edu [Source type: Reference]

^ In the x86 architecture, segmentation is an address translation step that the processor applies immediately before page translation.
• Vx32: Lightweight, User-level Sandboxing on the x86 11 January 2010 15:55 UTC pdos.csail.mit.edu [Source type: Reference]

.The 386 architecture became the basis of all further development in the x86 series.^ The mode provides full compatibility with all existing x86 architectures.
• A Glance at the Future: AMD Hammer Processors and x86-64 Technology - X-bit labs 11 January 2010 15:55 UTC www.xbitlabs.com [Source type: FILTERED WITH BAYES]

x86 processors that support protected mode boot into .real mode for backward compatibility with the older 8086 class of processors.^ To support both 32bit and 64bit code and registers, the x86-64 architecture allows the processor to work in two modes: Long Mode with two sub-modes (64bit and Compatibility modes) and Legacy Mode.
• A Glance at the Future: AMD Hammer Processors and x86-64 Technology - X-bit labs 11 January 2010 15:55 UTC www.xbitlabs.com [Source type: FILTERED WITH BAYES]

^ They are not supported in Solaris 2.6 or older, although they are recognized in its compatibility mode as regular ATAPI drives.
• Solaris on Intel - x86 FAQ 11 January 2010 15:55 UTC www.menet.umn.edu [Source type: FILTERED WITH BAYES]

.Upon power-on (aka booting), the processor initializes in real mode, and then begins executing machine code stored in ROM. An operating system boot sequence may place the processor into the Protected mode which enables paging and other features.^ This paper focuses on the vx32 virtual machine itself, describing its sandboxing technique in detail and analyzing its performance over a variety of applications, host operating systems, and hardware.
• Vx32: Lightweight, User-level Sandboxing on the x86 11 January 2010 15:55 UTC pdos.csail.mit.edu [Source type: Reference]

^ Vx32 performance is independent of the host operating system’s choice of processor mode, because vx32 always runs guest code in 32-bit mode.
• Vx32: Lightweight, User-level Sandboxing on the x86 11 January 2010 15:55 UTC pdos.csail.mit.edu [Source type: Reference]

^ Place all your profiles into learning mode with the following: aa-complain /etc/apparmor.d/* .
• Release Notes for SUSE Linux Enterprise Server 11 11 January 2010 15:55 UTC www.novell.com [Source type: FILTERED WITH BAYES]

.The instruction set in protected mode is backward compatible with the one used in real mode.^ Vx32 uses protected-mode segmentation, which has been integral to the x86 architecture since before its extension to 32 bits [21].
• Vx32: Lightweight, User-level Sandboxing on the x86 11 January 2010 15:55 UTC pdos.csail.mit.edu [Source type: Reference]

^ But unlike the 64bit mode, here the segmentation works as usual, using the protected mode semantics.
• A Glance at the Future: AMD Hammer Processors and x86-64 Technology - X-bit labs 11 January 2010 15:55 UTC www.xbitlabs.com [Source type: FILTERED WITH BAYES]

^ The entire situation is unfortunate since I [i]used [/i]to like the Acrobat format - that is, until I realized that it's no longer very cross platform compatible.
• OpenSolaris Forums : Adobe Acrobat for Solaris x86 ... 11 January 2010 15:55 UTC www.opensolaris.org [Source type: FILTERED WITH BAYES]

#### Virtual 8086 mode

.There is also a sub-mode of operation in 32-bit Protected mode, called virtual 8086 mode.^ Vx32 performance is independent of the host operating system’s choice of processor mode, because vx32 always runs guest code in 32-bit mode.
• Vx32: Lightweight, User-level Sandboxing on the x86 11 January 2010 15:55 UTC pdos.csail.mit.edu [Source type: Reference]

^ Compatibility mode provides binary compatibility of the existing 16- and 32-bit applications with the 64bit operation system.
• A Glance at the Future: AMD Hammer Processors and x86-64 Technology - X-bit labs 11 January 2010 15:55 UTC www.xbitlabs.com [Source type: FILTERED WITH BAYES]

^ To prove the fact that ClawHammer can easily run both 32- and 64-bit applications and operation systems, two systems with different OSs were demonstrated working.
• A Glance at the Future: AMD Hammer Processors and x86-64 Technology - X-bit labs 11 January 2010 15:55 UTC www.xbitlabs.com [Source type: FILTERED WITH BAYES]

.This is basically a special hybrid operating mode that allows real mode programs and operating systems to run while under the control of a Protected mode supervisor operating system.^ Vx32 runs guest code efficiently on several widespread operating systems without kernel extensions or special privileges; it protects the host program from both reads and writes by its guests; and it allows the host to restrict the instruction set available to guests.
• Vx32: Lightweight, User-level Sandboxing on the x86 11 January 2010 15:55 UTC pdos.csail.mit.edu [Source type: Reference]

^ Samba allows your system to act as a Windows server (even a domain controller) to Windows workstations.
• Installing Sun Solaris Intel 9 UNIX For x86 PC Installation 11 January 2010 15:55 UTC www.parkansky.com [Source type: General]

^ Vx32 performance is independent of the host operating system’s choice of processor mode, because vx32 always runs guest code in 32-bit mode.
• Vx32: Lightweight, User-level Sandboxing on the x86 11 January 2010 15:55 UTC pdos.csail.mit.edu [Source type: Reference]

.This allows for a great deal of flexibility in running both Protected mode programs and real mode programs simultaneously.^ Plan 9 VX (9vx for short) is a port of the Plan 9 operating system [35] to run on top of commodity operating systems, allowing the use of both Plan 9 and the host system simultaneously and also avoiding the need to write hardware drivers.
• Vx32: Lightweight, User-level Sandboxing on the x86 11 January 2010 15:55 UTC pdos.csail.mit.edu [Source type: Reference]

^ The running application views the processor as an ordinary x86 CPU in the protected mode.
• A Glance at the Future: AMD Hammer Processors and x86-64 Technology - X-bit labs 11 January 2010 15:55 UTC www.xbitlabs.com [Source type: FILTERED WITH BAYES]

^ To run user programs, 9vx creates an appropriate address space in a window within its own address space and invokes vx32 to simulate user mode execution.
• Vx32: Lightweight, User-level Sandboxing on the x86 11 January 2010 15:55 UTC pdos.csail.mit.edu [Source type: Reference]

.This mode is exclusively available for the 32-bit version of Protected mode; virtual 8086 mode does not exist previously in the 16-bit version of Protected mode, or in the 64-bit long mode.^ Also, values for MaxPClk for some cards are way too low in 16-bit and 24-bit modes in the /usr/openwin/share/etc/devdata/SUNWaccel/boards file.
• Solaris on Intel - x86 FAQ 11 January 2010 15:55 UTC www.menet.umn.edu [Source type: FILTERED WITH BAYES]

^ A big change in Solaris 7 is its support for 64-bit virtual addresses on UltraSPARCs, in contrast to 2.6 which has only 64-bit file offsets.
• Solaris on Intel - x86 FAQ 11 January 2010 15:55 UTC www.menet.umn.edu [Source type: FILTERED WITH BAYES]

^ To configure Xsun to use 16-bit color, configure using kdmconfig for the desired resolution in 256 color mode.
• Solaris on Intel - x86 FAQ 11 January 2010 15:55 UTC www.menet.umn.edu [Source type: FILTERED WITH BAYES]

### 64-bit Long mode

.By 2002, it was obvious that the 32-bit address space of the x86 architecture was limiting its performance in applications requiring large data sets.^ Vx32 performance is independent of the host operating system’s choice of processor mode, because vx32 always runs guest code in 32-bit mode.
• Vx32: Lightweight, User-level Sandboxing on the x86 11 January 2010 15:55 UTC pdos.csail.mit.edu [Source type: Reference]

^ In the x86 architecture, segmentation is an address translation step that the processor applies immediately before page translation.
• Vx32: Lightweight, User-level Sandboxing on the x86 11 January 2010 15:55 UTC pdos.csail.mit.edu [Source type: Reference]

^ Compatibility mode provides binary compatibility of the existing 16- and 32-bit applications with the 64bit operation system.
• A Glance at the Future: AMD Hammer Processors and x86-64 Technology - X-bit labs 11 January 2010 15:55 UTC www.xbitlabs.com [Source type: FILTERED WITH BAYES]

.A 32-bit address space would allow the processor to directly address only 4 Gb of data, a size surpassed by applications such as video processing and database engines, while using the 64-bit address, one can directly address 16777216 Tb (or 16 billion Gb) of data, although most 64-bit architectures don't support access to the full 64-bit address space (AMD64, for example, supports only 48 bits, split into 4 paging levels, from a 64-bit address).^ Create a new file using the text editor (click on File and then on New) and simply enter one IP address.
• Installing Sun Solaris Intel 9 UNIX For x86 PC Installation 11 January 2010 15:55 UTC www.parkansky.com [Source type: General]

^ To configure Xsun to use 16-bit color, configure using kdmconfig for the desired resolution in 256 color mode.
• Solaris on Intel - x86 FAQ 11 January 2010 15:55 UTC www.menet.umn.edu [Source type: FILTERED WITH BAYES]

^ Vx32 performance is independent of the host operating system’s choice of processor mode, because vx32 always runs guest code in 32-bit mode.
• Vx32: Lightweight, User-level Sandboxing on the x86 11 January 2010 15:55 UTC pdos.csail.mit.edu [Source type: Reference]

.AMD developed the extension of the 32-bit x86 architecture to 64-bit that is currently used in x86 processors, initially calling it x86-64, later renaming it AMD64.^ AMD developed for its Hammer processor family.
• A Glance at the Future: AMD Hammer Processors and x86-64 Technology - X-bit labs 11 January 2010 15:55 UTC www.xbitlabs.com [Source type: FILTERED WITH BAYES]

^ AMD used a similar approach to the development of the 64-bit architecture.
• A Glance at the Future: AMD Hammer Processors and x86-64 Technology - X-bit labs 11 January 2010 15:55 UTC www.xbitlabs.com [Source type: FILTERED WITH BAYES]

^ AMD x86-64 architecture programmer’s manual, September 2002.
• Vx32: Lightweight, User-level Sandboxing on the x86 11 January 2010 15:55 UTC pdos.csail.mit.edu [Source type: Reference]

.The Opteron, Athlon 64, Turion 64, and later Sempron families of processors use this architecture.^ The 64bit bus used in the Athlon CPU family looks a sort of out-dated and we tend to believe that this bus in Hammer will have at least 256bit width as Pentium 4 has.
• A Glance at the Future: AMD Hammer Processors and x86-64 Technology - X-bit labs 11 January 2010 15:55 UTC www.xbitlabs.com [Source type: FILTERED WITH BAYES]

^ AMD used a similar approach to the development of the 64-bit architecture.
• A Glance at the Future: AMD Hammer Processors and x86-64 Technology - X-bit labs 11 January 2010 15:55 UTC www.xbitlabs.com [Source type: FILTERED WITH BAYES]

^ For instance, Athlon XP is widely used in dual-processor systems where Athlon MP is supposed to be.
• A Glance at the Future: AMD Hammer Processors and x86-64 Technology - X-bit labs 11 January 2010 15:55 UTC www.xbitlabs.com [Source type: FILTERED WITH BAYES]

.The success of the AMD64 line of processors coupled with the lukewarm reception of the IA-64 architecture forced Intel to release their own implementation of the AMD64 instruction set.^ However, the CPU chips in Sun boxes are RISC chips (Reduced Instruction Set) so they are significantly faster than an Intel chip of a comparable clock speed.
• Installing Sun Solaris Intel 9 UNIX For x86 PC Installation 11 January 2010 15:55 UTC www.parkansky.com [Source type: General]

^ The shock was due to the fact that the only 64-bit processor then was Intel Itanium.
• A Glance at the Future: AMD Hammer Processors and x86-64 Technology - X-bit labs 11 January 2010 15:55 UTC www.xbitlabs.com [Source type: FILTERED WITH BAYES]

^ In contrast to the 64-bit IA64 architecture used in Intel Itanium processors, x86-64 is based on the existing x86-32 architecture.
• A Glance at the Future: AMD Hammer Processors and x86-64 Technology - X-bit labs 11 January 2010 15:55 UTC www.xbitlabs.com [Source type: FILTERED WITH BAYES]

.Intel had previously implemented support for AMD64[12] but opted not to enable it in hopes that AMD would not bring AMD64 to market before Itanium's new IA-64 instruction set was widely adopted.^ The shock was due to the fact that the only 64-bit processor then was Intel Itanium.
• A Glance at the Future: AMD Hammer Processors and x86-64 Technology - X-bit labs 11 January 2010 15:55 UTC www.xbitlabs.com [Source type: FILTERED WITH BAYES]

^ In contrast to the 64-bit IA64 architecture used in Intel Itanium processors, x86-64 is based on the existing x86-32 architecture.
• A Glance at the Future: AMD Hammer Processors and x86-64 Technology - X-bit labs 11 January 2010 15:55 UTC www.xbitlabs.com [Source type: FILTERED WITH BAYES]

^ "X86" refers to the set of machine language instructions that certain microprocessors from Intel and a few other companies execute.
• Happy birthday, x86! An industry standard turns 30 11 January 2010 15:55 UTC www.computerworld.com [Source type: News]

.They branded their implementation of AMD64 as EM64T, and later re-branded it Intel 64.^ What if they're not recompiled for new Intel Macs?

.In its literature and product version names, Microsoft and Sun refer to AMD64/Intel 64 collectively as x64 in the Windows and Solaris operating systems respectively.^ "Solaris" is the name of operating system product with all of the GUI stuff bundled in.
• Installing Sun Solaris Intel 9 UNIX For x86 PC Installation 11 January 2010 15:55 UTC www.parkansky.com [Source type: General]

^ But most people use the term Solaris when referring to Sun's operating system.
• Installing Sun Solaris Intel 9 UNIX For x86 PC Installation 11 January 2010 15:55 UTC www.parkansky.com [Source type: General]

^ Solaris x86 is a great operating system.

Linux distributions refer to it either as "x86-64", its variant "x86_64", or "amd64". BSD systems use "amd64" while Mac OS X uses "x86_64".
.Long mode is mostly an extension of the 32-bit instruction set, but unlike the 16–to–32-bit transition, many instructions were dropped in the 64 bit mode.^ That is, the 64bit mode is the 64-bitness as it is.
• A Glance at the Future: AMD Hammer Processors and x86-64 Technology - X-bit labs 11 January 2010 15:55 UTC www.xbitlabs.com [Source type: FILTERED WITH BAYES]

^ Also, values for MaxPClk for some cards are way too low in 16-bit and 24-bit modes in the /usr/openwin/share/etc/devdata/SUNWaccel/boards file.
• Solaris on Intel - x86 FAQ 11 January 2010 15:55 UTC www.menet.umn.edu [Source type: FILTERED WITH BAYES]

^ To configure Xsun to use 16-bit color, configure using kdmconfig for the desired resolution in 256 color mode.
• Solaris on Intel - x86 FAQ 11 January 2010 15:55 UTC www.menet.umn.edu [Source type: FILTERED WITH BAYES]

.This does not affect actual binary backward compatibility (which would execute legacy code in other modes that retain support for those instructions), but it changes the way assembler and compilers for new code have to work.^ It support WordPerfect, Word (old and new), HTML, RTF, FrameMaker, Applix, and several other document formats.
• Solaris on Intel - x86 FAQ 11 January 2010 15:55 UTC www.menet.umn.edu [Source type: FILTERED WITH BAYES]

^ Compatibility mode provides binary compatibility of the existing 16- and 32-bit applications with the 64bit operation system.
• A Glance at the Future: AMD Hammer Processors and x86-64 Technology - X-bit labs 11 January 2010 15:55 UTC www.xbitlabs.com [Source type: FILTERED WITH BAYES]

^ However, the operation system regards the mechanisms used for address translation, work with interrupts and exceptions, and system data structures as if they were of 64bit Long Mode; As an addition to Long mode, x86-64 is supposed to support Legacy mode thus providing binary compatibility with 16- and 32-bit operation systems.
• A Glance at the Future: AMD Hammer Processors and x86-64 Technology - X-bit labs 11 January 2010 15:55 UTC www.xbitlabs.com [Source type: FILTERED WITH BAYES]

.This was the first time that a major upgrade of the x86 architecture was initiated and originated by a manufacturer other than Intel.^ Phil Schiller Will I be able to run Windows/Linux/other x86 OS on my Intel Mac?

^ In contrast to the 64-bit IA64 architecture used in Intel Itanium processors, x86-64 is based on the existing x86-32 architecture.
• A Glance at the Future: AMD Hammer Processors and x86-64 Technology - X-bit labs 11 January 2010 15:55 UTC www.xbitlabs.com [Source type: FILTERED WITH BAYES]

^ I have been using the Solaris for last 10 years and all the time I have a difficulty with the fact that Adobe Reader is available for SPARC architecture only, and not for x86/x64.

It was also the first time that Intel accepted technology of this nature from an outside source.

## Extensions

### Floating point unit

.Initially, IA-32 included floating-point capabilities only on add-on processors (8087, 80287 and 80387.) With the introduction of the 80486, these 8 80x87 floating point registers, known as ST(0) through ST(7) are built in to the CPU. Each register is 80 bits wide and stores numbers in the double extended precision format of the IEEE floating-point standard.^ The shock was due to the fact that the only 64-bit processor then was Intel Itanium.
• A Glance at the Future: AMD Hammer Processors and x86-64 Technology - X-bit labs 11 January 2010 15:55 UTC www.xbitlabs.com [Source type: FILTERED WITH BAYES]

^ Of course, it won't solve the problem completely, but will reduce the number of critical situations of the kind, similar to the one described above (1-st processor - 8-th processor).
• A Glance at the Future: AMD Hammer Processors and x86-64 Technology - X-bit labs 11 January 2010 15:55 UTC www.xbitlabs.com [Source type: FILTERED WITH BAYES]

^ Also, some 64-bit x86 operating systems (e.g., Linux) use privileged instructions to initialize the thread-local segment register with a base that is impossible to represent in an ordinary 32-bit segment descriptor.
• Vx32: Lightweight, User-level Sandboxing on the x86 11 January 2010 15:55 UTC pdos.csail.mit.edu [Source type: Reference]

These registers are not accessible directly, but are accessible like a LIFO stack. The register numbers are not fixed, but are relative to the top of the stack; ST(0) is the top of the stack, ST(1) is the next register below the top of the stack, ST(2) is two below the top of the stack, etc. That means that data is always pushed down from the top of the stack, and operations are always done against the top of the stack. Register access had to be done in the stack order, not randomly.

### MMX

.MMX is a SIMD instruction set designed by Intel, introduced in 1997 for Pentium MMX microprocessors.^ However, the CPU chips in Sun boxes are RISC chips (Reduced Instruction Set) so they are significantly faster than an Intel chip of a comparable clock speed.
• Installing Sun Solaris Intel 9 UNIX For x86 PC Installation 11 January 2010 15:55 UTC www.parkansky.com [Source type: General]

^ "X86" refers to the set of machine language instructions that certain microprocessors from Intel and a few other companies execute.
• Happy birthday, x86! An industry standard turns 30 11 January 2010 15:55 UTC www.computerworld.com [Source type: News]

.It developed out of a similar unit first used on the Intel i860.^ AMD used a similar approach to the development of the 64-bit architecture.
• A Glance at the Future: AMD Hammer Processors and x86-64 Technology - X-bit labs 11 January 2010 15:55 UTC www.xbitlabs.com [Source type: FILTERED WITH BAYES]

^ I received my first Sun for home use in May 1986 for developing SCSI drivers.
• OpenSolaris Forums : Adobe Acrobat for Solaris x86 ... 11 January 2010 15:55 UTC www.opensolaris.org [Source type: FILTERED WITH BAYES]

^ In the first week of August 1986, I developed the first SCSI generic pass through system that is still in use for cdrecord.
• OpenSolaris Forums : Adobe Acrobat for Solaris x86 ... 11 January 2010 15:55 UTC www.opensolaris.org [Source type: FILTERED WITH BAYES]

It first appeared in the Pentium MMX. .It is supported on most subsequent IA-32 processors by Intel and other vendors.^ In contrast to the 64-bit IA64 architecture used in Intel Itanium processors, x86-64 is based on the existing x86-32 architecture.
• A Glance at the Future: AMD Hammer Processors and x86-64 Technology - X-bit labs 11 January 2010 15:55 UTC www.xbitlabs.com [Source type: FILTERED WITH BAYES]

^ Intel is rumored to be about to add x86-64 instructions support to Prescott (the Yamhill technology) as well as other innovations, which effect is hard to predict.
• A Glance at the Future: AMD Hammer Processors and x86-64 Technology - X-bit labs 11 January 2010 15:55 UTC www.xbitlabs.com [Source type: FILTERED WITH BAYES]

^ IA-32 Intel architecture software developer’s manual, June 2005.
• Vx32: Lightweight, User-level Sandboxing on the x86 11 January 2010 15:55 UTC pdos.csail.mit.edu [Source type: Reference]

MMX is typically used for video applications.
.MMX added 8 new "registers" to the architecture, known as MM0 through MM7 (henceforth referred to as MMn).^ Very simply: a few new registers were added to the register set, and the existing ones were extended: .
• A Glance at the Future: AMD Hammer Processors and x86-64 Technology - X-bit labs 11 January 2010 15:55 UTC www.xbitlabs.com [Source type: FILTERED WITH BAYES]

^ Eight new registers were added to the SSE unit to support SSE2.
• A Glance at the Future: AMD Hammer Processors and x86-64 Technology - X-bit labs 11 January 2010 15:55 UTC www.xbitlabs.com [Source type: FILTERED WITH BAYES]

.In reality, these new "registers" were just aliases for the existing x87 FPU stack registers.^ Very simply: a few new registers were added to the register set, and the existing ones were extended: .
• A Glance at the Future: AMD Hammer Processors and x86-64 Technology - X-bit labs 11 January 2010 15:55 UTC www.xbitlabs.com [Source type: FILTERED WITH BAYES]

.Hence, anything that was done to the floating point stack would also affect the MMX registers.^ To catch and isolate exceptions caused by guest code, vx32 needs to register its own signal handlers for processor exceptions such as segmentation faults and floating point exceptions.
• Vx32: Lightweight, User-level Sandboxing on the x86 11 January 2010 15:55 UTC pdos.csail.mit.edu [Source type: Reference]

Unlike the FP stack, these MMn registers were fixed, not relative, and therefore they were randomly accessible. .The instruction set did not adopt the stack-like semantics so that existing operating systems could still correctly save and restore the register state when multitasking without modifications.^ Compatibility mode provides binary compatibility of the existing 16- and 32-bit applications with the 64bit operation system.
• A Glance at the Future: AMD Hammer Processors and x86-64 Technology - X-bit labs 11 January 2010 15:55 UTC www.xbitlabs.com [Source type: FILTERED WITH BAYES]

^ Also, some 64-bit x86 operating systems (e.g., Linux) use privileged instructions to initialize the thread-local segment register with a base that is impossible to represent in an ordinary 32-bit segment descriptor.
• Vx32: Lightweight, User-level Sandboxing on the x86 11 January 2010 15:55 UTC pdos.csail.mit.edu [Source type: Reference]

^ We should make a note that there'll be enough of operation systems like that by the time Hammer hits the market.
• A Glance at the Future: AMD Hammer Processors and x86-64 Technology - X-bit labs 11 January 2010 15:55 UTC www.xbitlabs.com [Source type: FILTERED WITH BAYES]

Each of the MMn registers are 64-bit integers. .However, one of the main concepts of the MMX instruction set is the concept of packed data types, which means instead of using the whole register for a single 64-bit integer (quadword); two 32-bit integers (doubleword), four 16-bit integers (word) or eight 8-bit integers (byte) may be used.^ Two 32- and 64-bit versions were shown on a single screen simultaneously.
• A Glance at the Future: AMD Hammer Processors and x86-64 Technology - X-bit labs 11 January 2010 15:55 UTC www.xbitlabs.com [Source type: FILTERED WITH BAYES]

^ So, 64bit mode features the support of: 64bit virtual addresses; 8 new 64bit general-purpose registers; GPRs extension to 64bit (including the "old" EAX, EBX and so on); 64-bitinstruction pointer; New relative instruction pointer (RIP) method of data-addressing; Continuous address space with a single space for instructions, data and the stack.
• A Glance at the Future: AMD Hammer Processors and x86-64 Technology - X-bit labs 11 January 2010 15:55 UTC www.xbitlabs.com [Source type: FILTERED WITH BAYES]

^ However, the CPU chips in Sun boxes are RISC chips (Reduced Instruction Set) so they are significantly faster than an Intel chip of a comparable clock speed.
• Installing Sun Solaris Intel 9 UNIX For x86 PC Installation 11 January 2010 15:55 UTC www.parkansky.com [Source type: General]

.Also because the MMX's 64-bit MMn registers are aliased to the FPU stack, and each of the stack registers are 80-bit wide, the upper 16-bits of the stack registers go unused in MMX, and these bits are set to all ones, which makes it look like NaN's or infinities in the floating point view.^ EiB on all 64-bit architectures .
• Release Notes for SUSE Linux Enterprise Server 11 11 January 2010 15:55 UTC www.novell.com [Source type: FILTERED WITH BAYES]

^ View all newsletters * Valid e-mail address is required: E-mail Address: * Industry is required: Industry: Select One > > TECH .
• Happy birthday, x86! An industry standard turns 30 11 January 2010 15:55 UTC www.computerworld.com [Source type: News]

^ Besides, we know of at least one tricky issue with 2.6.30.x and the LILO bootloader, and the workaround that we know of likely isn't going to work on BIOSes older than 2001.
• The Slackware Linux Project: Slackware ChangeLogs 11 January 2010 15:55 UTC www.slackware.com [Source type: FILTERED WITH BAYES]

.This makes it easier to tell whether you are working on a floating point data or MMX data.^ To tell the truth, it will be much easier to build a chipset like that for Hammer: the integrated memory controller will save you a lot of time and trouble.
• A Glance at the Future: AMD Hammer Processors and x86-64 Technology - X-bit labs 11 January 2010 15:55 UTC www.xbitlabs.com [Source type: FILTERED WITH BAYES]

^ Provided you dedicate the people to make this work of course.
• OpenSolaris Forums : Adobe Acrobat for Solaris x86 ... 11 January 2010 15:55 UTC www.opensolaris.org [Source type: FILTERED WITH BAYES]

^ Of course, it's much easier to install CDE, if it works for you.
• Solaris on Intel - x86 FAQ 11 January 2010 15:55 UTC www.menet.umn.edu [Source type: FILTERED WITH BAYES]

### 3DNow!

In 1997 AMD introduced 3DNow! .The introduction of this technology coincided with the rise of 3D entertainment applications and was designed to improve the CPU's vector processing performance of graphic-intensive applications.^ How can I improve disk and graphic performance?
• Solaris on Intel - x86 FAQ 11 January 2010 15:55 UTC www.menet.umn.edu [Source type: FILTERED WITH BAYES]

^ This approach requires guest code to be written in a particular language, making it difficult to reuse existing legacy code or use advanced processor features such as vector instructions (SSE) to improve the performance of compute-intensive code.
• Vx32: Lightweight, User-level Sandboxing on the x86 11 January 2010 15:55 UTC pdos.csail.mit.edu [Source type: Reference]

.3D video game developers and 3D graphics hardware vendors use 3DNow!^ As a result, you'll see a lot of graphics accelerator video hardware available for these systems.
• Installing Sun Solaris Intel 9 UNIX For x86 PC Installation 11 January 2010 15:55 UTC www.parkansky.com [Source type: General]

^ If you don't have the time to deal with auctions, you can check out Web vendors of used Sun hardware on the Web.
• Installing Sun Solaris Intel 9 UNIX For x86 PC Installation 11 January 2010 15:55 UTC www.parkansky.com [Source type: General]

^ However, this intense graphics processing isn't needed with servers or administration workstations so don't waste money on high-end graphics cards when buying used hardware.
• Installing Sun Solaris Intel 9 UNIX For x86 PC Installation 11 January 2010 15:55 UTC www.parkansky.com [Source type: General]

to enhance their performance on .AMD's K6 and Athlon series of processors.^ The card has a 300 MHz K6-2 AMD processor and RAM. It emulates hard and floppy drives, serial ports, SuperVGA, mouse, keyboard, etc.
• Solaris on Intel - x86 FAQ 11 January 2010 15:55 UTC www.menet.umn.edu [Source type: FILTERED WITH BAYES]

^ Some time ago we got to know that AMD was preparing the launch of a new processor core, then called K8 (K7 - Athlon).
• A Glance at the Future: AMD Hammer Processors and x86-64 Technology - X-bit labs 11 January 2010 15:55 UTC www.xbitlabs.com [Source type: FILTERED WITH BAYES]

^ It served web-pages requested by the 8th generation AMD Athlon processor based computer.
• A Glance at the Future: AMD Hammer Processors and x86-64 Technology - X-bit labs 11 January 2010 15:55 UTC www.xbitlabs.com [Source type: FILTERED WITH BAYES]

3DNow! was designed to be the natural evolution of MMX from integers to floating point. .As such, it uses the exact same register naming convention as MMX, that is MM0 through MM7. The only difference is that instead of packing byte to quadword integers into these registers, one would pack single precision floating points into these registers.^ Only the would be eliminated by using a single-entry branch cache.
• Vx32: Lightweight, User-level Sandboxing on the x86 11 January 2010 15:55 UTC pdos.csail.mit.edu [Source type: Reference]

^ Which of these sound useful, and which would you contribute to?
• OpenSolaris Forums : Adobe Acrobat for Solaris x86 ... 11 January 2010 15:55 UTC www.opensolaris.org [Source type: FILTERED WITH BAYES]

^ Certain graphics, symbols, and terms used on this site and in its documents are registered trademarks of their respective owners and are contained herein for identification purposes only.
• Installing Sun Solaris Intel 9 UNIX For x86 PC Installation 11 January 2010 15:55 UTC www.parkansky.com [Source type: General]

.The advantage of aliasing registers with the FPU registers is that the same instruction and data structures used to save the state of the FPU registers can also be used to save 3DNow!^ Using both Ethernet and iSCSI functions at the same time may hang the device and cause data loss and filesystem corruptions on iSCSI devices, or network disruptions on Ethernet.
• Release Notes for SUSE Linux Enterprise Server 11 11 January 2010 15:55 UTC www.novell.com [Source type: FILTERED WITH BAYES]

^ The key to vx32’s combination of flexibility and efficiency is to use different mechanisms to sandbox data accesses and instruction execution.
• Vx32: Lightweight, User-level Sandboxing on the x86 11 January 2010 15:55 UTC pdos.csail.mit.edu [Source type: Reference]

^ The market has reacted to it by making the 'save as pdf' option to create portability, instead of using Adobe software for the same purpose.
• OpenSolaris Forums : Adobe Acrobat for Solaris x86 ... 11 January 2010 15:55 UTC www.opensolaris.org [Source type: FILTERED WITH BAYES]

register states. .Thus no special modifications are required to be made to operating systems which would otherwise not know about them.^ This section describes the requirements that vx32 places on its context—the processor, operating system, and guest code—and then explains the vx32 design.
• Vx32: Lightweight, User-level Sandboxing on the x86 11 January 2010 15:55 UTC pdos.csail.mit.edu [Source type: Reference]

^ I've tested this (requires amd64/EM64T on your system) > > Did you have to do anything special to get it to work?
• OpenSolaris Forums : Adobe Acrobat for Solaris x86 ... 11 January 2010 15:55 UTC www.opensolaris.org [Source type: FILTERED WITH BAYES]

^ Besides removing the hardware drivers, it required writing about 1,000 lines of code to interface with vx32, and another 500 to interface with the underlying host operating system.
• Vx32: Lightweight, User-level Sandboxing on the x86 11 January 2010 15:55 UTC pdos.csail.mit.edu [Source type: Reference]

### SSE

.In 1999, Intel introduced the Streaming SIMD Extensions (SSE) instruction set, following in 2000 with SSE2. The first addition allowed offloading of basic floating-point operations from the x87 stack and the second made MMX almost obsolete and allowed the instructions to be realistically targeted by conventional compilers.^ However, the CPU chips in Sun boxes are RISC chips (Reduced Instruction Set) so they are significantly faster than an Intel chip of a comparable clock speed.
• Installing Sun Solaris Intel 9 UNIX For x86 PC Installation 11 January 2010 15:55 UTC www.parkansky.com [Source type: General]

^ Decimal Floating Point and z10 instructions support .
• Release Notes for SUSE Linux Enterprise Server 11 11 January 2010 15:55 UTC www.novell.com [Source type: FILTERED WITH BAYES]

^ For Solaris 2.6 and 7 (2.5.1 instructions follow): First try, as root: "touch /reconfigure; /usr/sbin/reboot".
• Solaris on Intel - x86 FAQ 11 January 2010 15:55 UTC www.menet.umn.edu [Source type: FILTERED WITH BAYES]

.Introduced in 2004 along with the Prescott revision of the Pentium 4 processor, SSE3 added specific memory and thread-handling instructions to boost the performance of Intel's HyperThreading technology.^ The highest performance increase is expected from apps that make copious use of the memory and switch very often between the threads.
• A Glance at the Future: AMD Hammer Processors and x86-64 Technology - X-bit labs 11 January 2010 15:55 UTC www.xbitlabs.com [Source type: FILTERED WITH BAYES]

^ Moreover, all Intel multiprocessor systems (Xeon with its HyperThreading is among them) use the same SMP, which suppose that CPU bus and memory bandwidths are equally employed by the CPUs installed.
• A Glance at the Future: AMD Hammer Processors and x86-64 Technology - X-bit labs 11 January 2010 15:55 UTC www.xbitlabs.com [Source type: FILTERED WITH BAYES]

^ Moreover, the maximum memory size an application thread can use is equal to the same 4GB. That was one of the causes people started thinking of constructing 64bit processors.
• A Glance at the Future: AMD Hammer Processors and x86-64 Technology - X-bit labs 11 January 2010 15:55 UTC www.xbitlabs.com [Source type: FILTERED WITH BAYES]

.AMD licensed the SSE3 instruction set and implemented most of the SSE3 instructions for its revision E and later Athlon 64 processors.^ A Glance at the Future: AMD Hammer Processors and x86-64 Technology [08/14/2002 12:00 AM .
• A Glance at the Future: AMD Hammer Processors and x86-64 Technology - X-bit labs 11 January 2010 15:55 UTC www.xbitlabs.com [Source type: FILTERED WITH BAYES]

^ By the way, usually most processors of this revision cannot function at all!
• A Glance at the Future: AMD Hammer Processors and x86-64 Technology - X-bit labs 11 January 2010 15:55 UTC www.xbitlabs.com [Source type: FILTERED WITH BAYES]

^ Some time ago we got to know that AMD was preparing the launch of a new processor core, then called K8 (K7 - Athlon).
• A Glance at the Future: AMD Hammer Processors and x86-64 Technology - X-bit labs 11 January 2010 15:55 UTC www.xbitlabs.com [Source type: FILTERED WITH BAYES]

.The Athlon 64 does not support HyperThreading and lacks those SSE3 instructions used only for HyperThreading.^ A big change in Solaris 7 is its support for 64-bit virtual addresses on UltraSPARCs, in contrast to 2.6 which has only 64-bit file offsets.
• Solaris on Intel - x86 FAQ 11 January 2010 15:55 UTC www.menet.umn.edu [Source type: FILTERED WITH BAYES]

^ If the system was installed using the global version of the Live CD, which contins all supported languages, the pkg(1) command does not uninstall any package from the installed system.
• ReleaseNotes2008.11 (Project indiana.x86) - XWiki 11 January 2010 15:55 UTC hub.opensolaris.org [Source type: Reference]

^ Intel is rumored to be about to add x86-64 instructions support to Prescott (the Yamhill technology) as well as other innovations, which effect is hard to predict.
• A Glance at the Future: AMD Hammer Processors and x86-64 Technology - X-bit labs 11 January 2010 15:55 UTC www.xbitlabs.com [Source type: FILTERED WITH BAYES]

SSE discarded all legacy connections to the FPU stack. .This also meant that this instruction set discarded all legacy connections to previous generations of SIMD instruction sets like MMX. But it freed the designers up, allowing them to use larger registers, not limited by the size of the FPU registers.^ How can I use LILO to boot Solaris/x86 on the secondary master IDE? Follow the instructions for the previous question substituting /dev/hdc as directed.
• Solaris on Intel - x86 FAQ 11 January 2010 15:55 UTC www.menet.umn.edu [Source type: FILTERED WITH BAYES]

^ Look: Work at much higher core clock resulting in better performance; High-speed bus (533MHz) and memory (up to RDRAM PC1066) subsystems; SSE2 instructions set; Larger L2 cache.
• A Glance at the Future: AMD Hammer Processors and x86-64 Technology - X-bit labs 11 January 2010 15:55 UTC www.xbitlabs.com [Source type: FILTERED WITH BAYES]

^ I would consider this book (or one like it) a necessity if you want to set up a serious Web server.
• Installing Sun Solaris Intel 9 UNIX For x86 PC Installation 11 January 2010 15:55 UTC www.parkansky.com [Source type: General]

.The designers created eight 128-bit registers, named XMM0 through XMM7. (Note: in AMD64, the number of SSE XMM registers has been increased from 8 to 16.) However, the downside was that operating systems had to have an awareness of this new set of instructions in order to be able to save their register states.^ Eight new registers were added to the SSE unit to support SSE2.
• A Glance at the Future: AMD Hammer Processors and x86-64 Technology - X-bit labs 11 January 2010 15:55 UTC www.xbitlabs.com [Source type: FILTERED WITH BAYES]

^ However, the CPU chips in Sun boxes are RISC chips (Reduced Instruction Set) so they are significantly faster than an Intel chip of a comparable clock speed.
• Installing Sun Solaris Intel 9 UNIX For x86 PC Installation 11 January 2010 15:55 UTC www.parkansky.com [Source type: General]

^ Compatibility mode provides binary compatibility of the existing 16- and 32-bit applications with the 64bit operation system.
• A Glance at the Future: AMD Hammer Processors and x86-64 Technology - X-bit labs 11 January 2010 15:55 UTC www.xbitlabs.com [Source type: FILTERED WITH BAYES]

.So Intel created a slightly modified version of Protected mode, called Enhanced mode which enables the usage of SSE instructions, whereas they stay disabled in regular Protected mode.^ However, the CPU chips in Sun boxes are RISC chips (Reduced Instruction Set) so they are significantly faster than an Intel chip of a comparable clock speed.
• Installing Sun Solaris Intel 9 UNIX For x86 PC Installation 11 January 2010 15:55 UTC www.parkansky.com [Source type: General]

^ The thing is that Adobe does create new versions of their software in > > > less time than you state, just that they don't do it for Solaris on x86.
• OpenSolaris Forums : Adobe Acrobat for Solaris x86 ... 11 January 2010 15:55 UTC www.opensolaris.org [Source type: FILTERED WITH BAYES]

^ The thing is that Adobe does create new versions of their software in > > less time than you state, just that they don't do it for Solaris on x86.
• OpenSolaris Forums : Adobe Acrobat for Solaris x86 ... 11 January 2010 15:55 UTC www.opensolaris.org [Source type: FILTERED WITH BAYES]

.An OS that is aware of SSE will activate Enhanced mode, whereas an unaware OS will only enter into traditional Protected mode.^ The OS will boot in the 64-bit mode only if the system has atleast 1000 MB of RAM. Systems with less than this amount will boot in the 32-bit mode.
• ReleaseNotes2008.11 (Project indiana.x86) - XWiki 11 January 2010 15:55 UTC hub.opensolaris.org [Source type: Reference]

^ AGP controller remains the only thing left from the traditional North Bridge and it can be easily implemented into the South Bridge chip.
• A Glance at the Future: AMD Hammer Processors and x86-64 Technology - X-bit labs 11 January 2010 15:55 UTC www.xbitlabs.com [Source type: FILTERED WITH BAYES]

.SSE is a SIMD instruction set that works only on floating point values, like 3DNow!.^ Decimal Floating Point and z10 instructions support .
• Release Notes for SUSE Linux Enterprise Server 11 11 January 2010 15:55 UTC www.novell.com [Source type: FILTERED WITH BAYES]

^ For example, for consistent behavior across processor implementations, the VXA archiver described in Section 5.1 disallows the non-deterministic 387 floating-point instructions, forcing applications to use deterministic SSE-based equivalents.
• Vx32: Lightweight, User-level Sandboxing on the x86 11 January 2010 15:55 UTC pdos.csail.mit.edu [Source type: Reference]

^ Jumps are the only instructions whose translated size is not known exactly at this point.
• Vx32: Lightweight, User-level Sandboxing on the x86 11 January 2010 15:55 UTC pdos.csail.mit.edu [Source type: Reference]

However, unlike 3DNow! it severs all legacy connection to the FPU stack. .Because it has larger registers than 3DNow!, SSE can pack twice the number of single precision floats into its registers.^ In fact, 9vx’s simulation of system calls is faster than VMware’s and QEMU’s, because it doesn’t require simulating the processor’s entry into and exit from kernel mode.
• Vx32: Lightweight, User-level Sandboxing on the x86 11 January 2010 15:55 UTC pdos.csail.mit.edu [Source type: Reference]

The original SSE was limited to only single-precision numbers, like 3DNow!. The SSE2 introduced the capability to pack double precision numbers too, which 3DNow! had no possibility of doing since a double precision number is 64-bit in size which would be the full size of a single 3DNow! MMn register. .At 128-bit, the SSE XMMn registers could pack two double precision floats into one register.^ During any memory access, the processor uses the value in one of these segment registers as an index into one of two segment translation tables, the global descriptor table (GDT) or local descriptor table (LDT).
• Vx32: Lightweight, User-level Sandboxing on the x86 11 January 2010 15:55 UTC pdos.csail.mit.edu [Source type: Reference]

^ It is common nowadays for thread libraries to use one of these two segment registers— fs or gs —as a pointer to thread-local storage.
• Vx32: Lightweight, User-level Sandboxing on the x86 11 January 2010 15:55 UTC pdos.csail.mit.edu [Source type: Reference]

.Thus SSE2 is much more suitable for scientific calculations than either SSE1 or 3DNow!, which were limited to only single precision.^ The latter two uses require much more complex code transformations than vx32 performs, with a correspondingly larger performance cost [37].
• Vx32: Lightweight, User-level Sandboxing on the x86 11 January 2010 15:55 UTC pdos.csail.mit.edu [Source type: Reference]

^ What I also noticed was, that Evince is so much more lightweight, than fat and sluggish Acroread 8.x (SPARC).
• OpenSolaris Forums : Adobe Acrobat for Solaris x86 ... 11 January 2010 15:55 UTC www.opensolaris.org [Source type: FILTERED WITH BAYES]

^ Data compression algorithms evolve much more rapidly than processor architectures, so VXA packages executable decoders into the compressed archives along with the compressed data itself.
• Vx32: Lightweight, User-level Sandboxing on the x86 11 January 2010 15:55 UTC pdos.csail.mit.edu [Source type: Reference]

SSE3 does not introduce any additional registers.

.By default, physical addresses are 32-bit; but there exists a page extension mode called Physical Address Extension or PAE, first added in the Intel Pentium Pro, which allows an additional 4 bits of physical addressing.^ Vx32 performance is independent of the host operating system’s choice of processor mode, because vx32 always runs guest code in 32-bit mode.
• Vx32: Lightweight, User-level Sandboxing on the x86 11 January 2010 15:55 UTC pdos.csail.mit.edu [Source type: Reference]

^ The first argument is the target eip ; the second is the address of the end of the 32-bit jump offset to be patched.
• Vx32: Lightweight, User-level Sandboxing on the x86 11 January 2010 15:55 UTC pdos.csail.mit.edu [Source type: Reference]

^ Vx32 uses protected-mode segmentation, which has been integral to the x86 architecture since before its extension to 32 bits [21].
• Vx32: Lightweight, User-level Sandboxing on the x86 11 January 2010 15:55 UTC pdos.csail.mit.edu [Source type: Reference]

The size of memory in Protected mode is usually limited to 4 GB. .Through tricks in the processor's page and segment memory management systems, x86 operating systems may be able to access more than 32-bits of address space, even without the switchover to the 64-bit paradigm.^ As the memory is accessed through the processor in all Hammer systems, it may negatively tell on the GPU performance.
• A Glance at the Future: AMD Hammer Processors and x86-64 Technology - X-bit labs 11 January 2010 15:55 UTC www.xbitlabs.com [Source type: FILTERED WITH BAYES]

^ Upon finding the appropriate descriptor table entry, the processor checks permission bits (read, write, and execute) and compares the virtual address of the requested memory access against the segment limit in the descriptor table, throwing an exception if any of these checks fail.
• Vx32: Lightweight, User-level Sandboxing on the x86 11 January 2010 15:55 UTC pdos.csail.mit.edu [Source type: Reference]

^ Even under a 64-bit operating system, the processor switches to 32-bit mode when executing vx32’s 32-bit code segments, so vx32’s execution time is essentially identical in each case.
• Vx32: Lightweight, User-level Sandboxing on the x86 11 January 2010 15:55 UTC pdos.csail.mit.edu [Source type: Reference]

.This mode does not change the length of segment offsets or linear addresses; those are still only 32 bits.^ A big change in Solaris 7 is its support for 64-bit virtual addresses on UltraSPARCs, in contrast to 2.6 which has only 64-bit file offsets.
• Solaris on Intel - x86 FAQ 11 January 2010 15:55 UTC www.menet.umn.edu [Source type: FILTERED WITH BAYES]

^ Vx32 performance is independent of the host operating system’s choice of processor mode, because vx32 always runs guest code in 32-bit mode.
• Vx32: Lightweight, User-level Sandboxing on the x86 11 January 2010 15:55 UTC pdos.csail.mit.edu [Source type: Reference]

^ Compatibility mode provides binary compatibility of the existing 16- and 32-bit applications with the 64bit operation system.
• A Glance at the Future: AMD Hammer Processors and x86-64 Technology - X-bit labs 11 January 2010 15:55 UTC www.xbitlabs.com [Source type: FILTERED WITH BAYES]

### x64

.On April 2003, AMD released the first x86 processor with 64-bit physical memory address registers that was theoretically capable of employing 16 EiB of memory using the new x86-64 extension (also known as x64).^ AMD used a similar approach to the development of the 64-bit architecture.
• A Glance at the Future: AMD Hammer Processors and x86-64 Technology - X-bit labs 11 January 2010 15:55 UTC www.xbitlabs.com [Source type: FILTERED WITH BAYES]

^ What's new for release 7 of Solaris/x86?
• Solaris on Intel - x86 FAQ 11 January 2010 15:55 UTC www.menet.umn.edu [Source type: FILTERED WITH BAYES]

^ But first, let's think what do we actually need 64-bit processors for?
• A Glance at the Future: AMD Hammer Processors and x86-64 Technology - X-bit labs 11 January 2010 15:55 UTC www.xbitlabs.com [Source type: FILTERED WITH BAYES]

Intel introduced its first x86-64 processor on July 2004.
x86-64 was not the first architecture to employ .64-bit memory addressing architecture: Intel had already introduced Itanium in 2001 for high-performance computing market.^ EiB on all 64-bit architectures .
• Release Notes for SUSE Linux Enterprise Server 11 11 January 2010 15:55 UTC www.novell.com [Source type: FILTERED WITH BAYES]

^ A big change in Solaris 7 is its support for 64-bit virtual addresses on UltraSPARCs, in contrast to 2.6 which has only 64-bit file offsets.
• Solaris on Intel - x86 FAQ 11 January 2010 15:55 UTC www.menet.umn.edu [Source type: FILTERED WITH BAYES]

^ Solaris/x86 7 should support Intel's Extended Server Memory Architecture, with its 36-bit physical memory addresses (64 GBmemory), on Pentium Pro, Pentium II Xeon, and beyond.
• Solaris on Intel - x86 FAQ 11 January 2010 15:55 UTC www.menet.umn.edu [Source type: FILTERED WITH BAYES]

.However, Itanium was incompatible with x86. Another significance of x86-64 was the introduction of NX bit, a feature that offers stronger protection against malicious programs.^ The shock was due to the fact that the only 64-bit processor then was Intel Itanium.
• A Glance at the Future: AMD Hammer Processors and x86-64 Technology - X-bit labs 11 January 2010 15:55 UTC www.xbitlabs.com [Source type: FILTERED WITH BAYES]

^ Vx32 uses protected-mode segmentation, which has been integral to the x86 architecture since before its extension to 32 bits [21].
• Vx32: Lightweight, User-level Sandboxing on the x86 11 January 2010 15:55 UTC pdos.csail.mit.edu [Source type: Reference]

^ "Sun injects Solaris X86 with new life as it makes its way to 64 bits" Sun World .
• Solaris on Intel - x86 FAQ 11 January 2010 15:55 UTC www.menet.umn.edu [Source type: FILTERED WITH BAYES]

## Virtualization

Until recently, the x86 architecture did not meet the Popek and Goldberg requirements - a specification for virtualization created in 1974 by Gerald J. Popek and Robert P. Goldberg. .Nevertheless, there are several commercial x86 virtualization products, such as VMware vSphere, Parallels, Microsoft Hyper-V Server, and Microsoft Virtual PC.^ In such memory scenarios we strongly recommend using a x86-64 system with 64-bit SUSE Linux Enterprise Server, and run the (32bit) x86 applications on it.
• Release Notes for SUSE Linux Enterprise Server 11 11 January 2010 15:55 UTC www.novell.com [Source type: FILTERED WITH BAYES]

^ Solaris x86 is the version that runs on Intel-based PCs and servers.
• Solaris on Intel - x86 FAQ 11 January 2010 15:55 UTC www.menet.umn.edu [Source type: FILTERED WITH BAYES]

.Among the open source virtualization projects, most notable are QEMU/KQEMU, VirtualBox, and Xen.^ With the SUSE Linux Enterprise High Availability Extension 11 , Novell offers the most modern open source High Availability Stack for Mission Critical environments.
• Release Notes for SUSE Linux Enterprise Server 11 11 January 2010 15:55 UTC www.novell.com [Source type: FILTERED WITH BAYES]

.Intel and AMD have introduced x86 processors with hardware-based virtualization extensions that overcome the classical virtualization limitations of the x86 architecture.^ In the x86 architecture, segmentation is an address translation step that the processor applies immediately before page translation.
• Vx32: Lightweight, User-level Sandboxing on the x86 11 January 2010 15:55 UTC pdos.csail.mit.edu [Source type: Reference]

^ AMD x86-64 architecture programmer’s manual, September 2002.
• Vx32: Lightweight, User-level Sandboxing on the x86 11 January 2010 15:55 UTC pdos.csail.mit.edu [Source type: Reference]

^ Vx32 uses protected-mode segmentation, which has been integral to the x86 architecture since before its extension to 32 bits [21].
• Vx32: Lightweight, User-level Sandboxing on the x86 11 January 2010 15:55 UTC pdos.csail.mit.edu [Source type: Reference]

.These extensions are known as Intel VT (code named "Vanderpool",) and AMD-V (code named "Pacifica".) Although most modern x86 processors include these extensions, the technology is generally considered immature at this point with most software-based virtualization outperforming these extensions.^ Although these features are not strictly required by vx32, they are, once again, provided by all widely-used x86 operating systems.
• Vx32: Lightweight, User-level Sandboxing on the x86 11 January 2010 15:55 UTC pdos.csail.mit.edu [Source type: Reference]

^ Thus, a normal segment with base b and limit l permits memory accesses at virtual addresses between 0 and l , and maps these virtual addresses to linear addresses from b to b + l .
• Vx32: Lightweight, User-level Sandboxing on the x86 11 January 2010 15:55 UTC pdos.csail.mit.edu [Source type: Reference]

^ These mechanisms still require kernel modifications, however, which are not easily portable even between different x86-based OSes.
• Vx32: Lightweight, User-level Sandboxing on the x86 11 January 2010 15:55 UTC pdos.csail.mit.edu [Source type: Reference]

[13] This is expected to change as the technology matures.

## Notes

.
• Vx32: Lightweight, User-level Sandboxing on the x86 11 January 2010 15:55 UTC pdos.csail.mit.edu [Source type: Reference]

.^ This paper focuses on the vx32 virtual machine itself, describing its sandboxing technique in detail and analyzing its performance over a variety of applications, host operating systems, and hardware.
• Vx32: Lightweight, User-level Sandboxing on the x86 11 January 2010 15:55 UTC pdos.csail.mit.edu [Source type: Reference]

^ A comparison of software and hardware techniques for x86 virtualization.
• Vx32: Lightweight, User-level Sandboxing on the x86 11 January 2010 15:55 UTC pdos.csail.mit.edu [Source type: Reference]

^ The vx32 virtual machine separates data sandboxing from code sandboxing, using different, complementary mechanisms for each: x86 segmentation hardware to sandbox data references and dynamic instruction translation to sandbox code.
• Vx32: Lightweight, User-level Sandboxing on the x86 11 January 2010 15:55 UTC pdos.csail.mit.edu [Source type: Reference]

.Proceedings of the International Conference on Architectural Support for Programming Languages and Operating Systems, San Jose, CA, USA, 2006. ACM 1-59593-451-0/06/0010.^ The system call interface is complete enough to support the SPEC CPU2006 integer benchmark programs, which we ran both using vx32 (vxrun) and natively.
• Vx32: Lightweight, User-level Sandboxing on the x86 11 January 2010 15:55 UTC pdos.csail.mit.edu [Source type: Reference]

^ ACM SIGOPS Operating Systems Review , 27(5):203–216, December 1993.
• Vx32: Lightweight, User-level Sandboxing on the x86 11 January 2010 15:55 UTC pdos.csail.mit.edu [Source type: Reference]

^ Posts: 14 From: San Luis Obispo, CA Registered: 10/12/06 .
• OpenSolaris Forums : Adobe Acrobat for Solaris x86 ... 11 January 2010 15:55 UTC www.opensolaris.org [Source type: FILTERED WITH BAYES]

.http://www.vmware.com/pdf/asplos235_adams.pdf.^ See http://www.BootManager.com/ System Selector needs a small FAT or FAT32 partition to install on.
• Solaris on Intel - x86 FAQ 11 January 2010 15:55 UTC www.menet.umn.edu [Source type: FILTERED WITH BAYES]

^ You can get the free GNU C compiler, gcc, from various locations, including http://www.sunfreeware.com/ in pkgadd format.
• Solaris on Intel - x86 FAQ 11 January 2010 15:55 UTC www.menet.umn.edu [Source type: FILTERED WITH BAYES]

^ For information, see http://www.ugcs.caltech.edu/~steven/lxrun/ and http://ftp.sco.com/skunkware/emulators/lxrun/ .
• Solaris on Intel - x86 FAQ 11 January 2010 15:55 UTC www.menet.umn.edu [Source type: FILTERED WITH BAYES]

.Retrieved 2006-12-22.

• Rosenblum, Mendel; Garfinkel, Tal (May, 2005).^ May-2006 06:22 .
• Index of /ftp/fedora/linux/updates/5/x86_64 11 January 2010 15:55 UTC limestone.uoregon.edu [Source type: Academic]

^ Re: Re: Adobe Acrobat for Solaris x86 Posted: May 27, 2006 12:05 PM   in response to: wesw .
• OpenSolaris Forums : Adobe Acrobat for Solaris x86 ... 11 January 2010 15:55 UTC www.opensolaris.org [Source type: FILTERED WITH BAYES]

^ Re: Adobe Acrobat for Solaris x86 Posted: May 28, 2006 12:09 AM   in response to: aland .
• OpenSolaris Forums : Adobe Acrobat for Solaris x86 ... 11 January 2010 15:55 UTC www.opensolaris.org [Source type: FILTERED WITH BAYES]

"Virtual machine monitors: current technology and future trends". IEEE Computer, volume 38, issue 5.

## References

1. ^ Unlike the microarchitecture (and specific electronic and physical implementation) used for a specific chip design.
2. ^ Intel abandoned its "x86" naming scheme with the Pentium in 1993 (as numbers could not be trademarked). However, the term x86 was already firmly established among technicians, compiler writers etc.
3. ^ Intel's naming are IA-32 and Intel 64 (formerly EM64T or IA-32e) for x86 and x86-64 respectively. Likewise, AMD today prefers AMD64 over the x86-64 name they once introduced.
4. ^ "Linux* Kernel Compiling". Intel. Retrieved 2007-09-04.
5. ^
6. ^ The embedded processor's market is populated by more than 25 different architectures, which, due to the price sensitivity, low power and hardware simplicity requirements, outnumber the x86.
7. ^ "Microprocessor Hall of Fame". Intel. Retrieved 2007-08-11.
8. ^ The NEC V20 and V30 also provided the older 8080 instruction set, allowing PC equipped with these chips to run CP/M applications at full speed (i.e. without the need to simulate a 8080 in software).
9. ^ It had a slower Floating point unit however, which is slightly ironic as Cyrix started out as a designer of fast Floating point units for x86 processors.
10. ^ 16-bit and 32-bit chips were introduced in 1978 and 1985 respectively; plans for 64-bit was announced in 1999 and gradually introduced from 2003 and onwards.
11. ^ That is because integer arithmetics generates carry between subsequent bits (unlike simple bitwise operations).
12. ^ Intel's Yamhill Technology: x86-64 compatible | Geek.com
13. ^ A Comparison of Software and Hardware Techniques for x86 Virtualization

# Wikibooks

Up to date as of January 23, 2010
(Redirected to x86 Assembly article)

x86 Assembly

## Preface

.This book covers assembly language programming for the x86 family of microprocessors.^ This course covers the basics of programming in the x86 assembly language.
• MindShare - x86 Assembly Language Programming (Training) 11 January 2010 15:55 UTC mindshare.com [Source type: Reference]

^ Learn > x86 Assembly Language Programming .
• MindShare - x86 Assembly Language Programming (Training) 11 January 2010 15:55 UTC mindshare.com [Source type: Reference]

^ Assembly language programming tools review.
• Google Directory - Computers > Programming > Languages > Assembly > x86 11 January 2010 15:55 UTC directory.google.com [Source type: Reference]

.The objective is to teach how to program in x86 assembly, as well as the history and basic architecture of x86 processor family.^ This book covers assembly language programming for the x86 family of microprocessors.
• x86 Assembly - Wikibooks, collection of open-content textbooks 11 January 2010 15:55 UTC en.wikibooks.org [Source type: Reference]
• x86 Assembly - Wikibooks, collection of open-content textbooks 11 January 2010 15:55 UTC ja.wikibooks.org [Source type: Reference]

^ The objective is to teach how to program in x86 assembly, as well as the history and basic architecture of x86 processor family.
• x86 Assembly - Wikibooks, collection of open-content textbooks 11 January 2010 15:55 UTC en.wikibooks.org [Source type: Reference]
• x86 Assembly - Wikibooks, collection of open-content textbooks 11 January 2010 15:55 UTC ja.wikibooks.org [Source type: Reference]

^ Basic Principles of x86-64 Architecture .
• A Glance at the Future: AMD Hammer Processors and x86-64 Technology - X-bit labs 11 January 2010 15:55 UTC www.xbitlabs.com [Source type: FILTERED WITH BAYES]

.When referring to x86 we address the complete range of x86-based processors but keep in mind that x86-32 Assembly is commonly referred to as IA-32 (Intel Architecture, 32-bit) Assembly, a 32-bit extension of the original Intel x86 processor architecture.^ Intro to 32/64-bit x86 Architecture .
• MindShare - Intel 32/64-bit x86 Architecture (Training) 11 January 2010 15:55 UTC mindshare.com [Source type: General]

^ Comprehensive Intel 32/64-bit x86 Architecture Course Info .
• MindShare - Intel 32/64-bit x86 Architecture (Training) 11 January 2010 15:55 UTC mindshare.com [Source type: General]

^ Table 3 Processor registers in the IA-32 architecture .
• Mac Dev Center: Mac OS X ABI Function Call Guide: IA-32 Function Calling Conventions 11 January 2010 15:55 UTC developer.apple.com [Source type: Reference]

.IA-32 has full backwards compatibility (16-bit).^ Had a full 16 bit external bus.
• x86@Everything2.com 11 January 2010 15:55 UTC www.everything2.com [Source type: FILTERED WITH BAYES]

^ IA-32 has full backwards compatibility (16-bit).
• x86 Assembly - Wikibooks, collection of open-content textbooks 11 January 2010 15:55 UTC en.wikibooks.org [Source type: Reference]
• x86 Assembly - Wikibooks, collection of open-content textbooks 11 January 2010 15:55 UTC ja.wikibooks.org [Source type: Reference]

^ Family x86 Architecture and register description Comments 16, 32 and 64 Bits Intrinsic Data Types [ edit ] x86 Instruction Set .
• x86 Assembly - Wikibooks, collection of open-content textbooks 11 January 2010 15:55 UTC en.wikibooks.org [Source type: Reference]
• x86 Assembly - Wikibooks, collection of open-content textbooks 11 January 2010 15:55 UTC ja.wikibooks.org [Source type: Reference]

.AMD64 or AMD 64-bit extension is called x86-64 and is backwards compatible with 32-bit code without performance loss.^ Intro to 32/64-bit x86 Architecture .
• MindShare - Intel 32/64-bit x86 Architecture (Training) 11 January 2010 15:55 UTC mindshare.com [Source type: General]

^ AMD64 or AMD 64-bit extension is called x86-64 and is backwards compatible with 32-bit code without performance loss.
• x86 Assembly - Wikibooks, collection of open-content textbooks 11 January 2010 15:55 UTC en.wikibooks.org [Source type: Reference]
• x86 Assembly - Wikibooks, collection of open-content textbooks 11 January 2010 15:55 UTC ja.wikibooks.org [Source type: Reference]

^ And not all 32-bit processors are x86.
• Why is 32bit called x86 and not x32? - PC World Forums 11 January 2010 15:55 UTC forums.pcworld.com [Source type: General]

.Intel 64 previously named IA-32e or EM64T is almost identical to x86-64. Throughout the book these terms may be used interchangeably when appropriate.^ Throughout the book these terms may be used interchangeably when appropriate.
• x86 Assembly - Wikibooks, collection of open-content textbooks 11 January 2010 15:55 UTC en.wikibooks.org [Source type: Reference]
• x86 Assembly - Wikibooks, collection of open-content textbooks 11 January 2010 15:55 UTC ja.wikibooks.org [Source type: Reference]

^ Intel 64 previously named IA-32e or EM64T is almost identical to x86-64.
• x86 Assembly - Wikibooks, collection of open-content textbooks 11 January 2010 15:55 UTC en.wikibooks.org [Source type: Reference]
• x86 Assembly - Wikibooks, collection of open-content textbooks 11 January 2010 15:55 UTC ja.wikibooks.org [Source type: Reference]

^ This architecture was originally referred to as EM64T. Because the Intel 64 instruction set is a superset of the IA32 (x86) instruction set, all instructions in the x86 instruction set can be executed by CPUs that implement Intel 64; therefore those CPUs can natively run programs that run on x86 processors from Intel, AMD and other vendors.
• MindShare - Intel 32/64-bit x86 Architecture (Training) 11 January 2010 15:55 UTC mindshare.com [Source type: General]

.A special notice will be given if covering 16-bit, 32-bit or 64-bits architectures and on any limitations so to limit confusion.^ Instruction Set Architecture: Comprehensive 32/64-bit Coverage .
• MindShare - x86 Assembly Language Programming (Training) 11 January 2010 15:55 UTC mindshare.com [Source type: Reference]

^ Solaris x86 32 bit and 64 bit .
• What are the system requirements for Java 6? 11 January 2010 15:55 UTC java.com [Source type: FILTERED WITH BAYES]

^ Intro to 32/64-bit x86 Architecture eLearning Course .
• MindShare - x86 Assembly Language Programming (Training) 11 January 2010 15:55 UTC mindshare.com [Source type: Reference]

# Simple English

x86 is a term used to describe an instruction set compatible with the Intel 8086's.

# Citable sentences

Up to date as of December 30, 2010

Here are sentences from other pages on X86, which are similar to those in the above article.